Integrated Decoupling Capacitor Fabrication Using Handle Wafer Support
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Solution Overview
Problem
Existing methods for fabricating integrated passives, such as capacitors, are complex, fail to meet demands for compact, low-profile applications, and often require large solder bumps and inefficient use of space, especially in high-density IC assemblies like cell phones and processors.
Innovation Solution
A method involving a silicon wafer with a high-quality thermal oxide layer and a conductive metal layer, where a handle wafer is used to support the capacitor wafer during processing, allowing for thinning and the deposition of additional conductive layers, ultimately minimizing package thickness and eliminating solder bumps through the use of a releasable adhesive like BCB or acrylic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If integrated passives are fabricated using known methods, then capacitance capability can be achieved, but the fabrication process becomes complicated and requires unusual processing sequences
Solution Approach 1:
The patent introduces a handle wafer as an intermediary substrate to simplify the fabrication process. The handle wafer provides a stable platform for fabricating the capacitor structure, allowing standard semiconductor processing techniques to be used without requiring unusual processing sequences. After fabrication, the handle wafer is removed, leaving the capacitor structure intact.
Solution Approach 2:
The fabrication process is segmented into distinct stages: first fabricating the capacitor structure on the handle wafer, then removing the handle wafer as a separate step. This segmentation allows each stage to be optimized independently, simplifying the overall process while maintaining capacitance capability.
2Area of stationary object
If integrated passives are integrated into IC substrates to achieve denser assemblies, then space requirements are reduced, but the profile height increases
Solution Approach 1:
The patent employs thin film techniques to create the capacitor structure, using deposited metal layers and oxide layers that are extremely thin. This allows the capacitor to achieve the required capacitance in a compact volume with minimal profile height, while still providing dense assembly integration.
3Reliability
If solder bumps are used to mount capacitors on IC surfaces, then electrical connections are established, but production costs increase and space requirements increase
Solution Approach 1:
The patent merges the capacitor structure directly with the IC substrate using thin film deposition techniques, eliminating the need for separate solder bump mounting. The capacitor electrodes are formed as integrated structures that make direct electrical contact with the IC, reducing both production costs and space requirements while maintaining reliable electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of high-quality, thin integrated capacitors with low parasitic losses and high reliability, maximizing capacitance while minimizing production costs and space requirements, suitable for dense IC assemblies with improved electrical and physical characteristics.
Implementation Method 1
providing an oxide layer on the topside of the capacitor wafer
Implementation Method 2
provide, such as by deposition or sputtering, a high quality metal layer
Implementation Method 3
providing an adhesive on the topside of the handle wafer for adhering the topside of the handle wafer to the topside of the oxide layer
Data Source
AI summary
Method of making an integrated passive, such as a high quality decoupling capacitor, includes providing a first temporary support, a silicon capacitor wafer, and providing an oxide layer and a conductive layer on it. Then, a second temporary support, such as a handle wafer, may be attached to the capacitor wafer (i.e., to the oxide layer on it) by an adhesive bond. The capacitor wafer may then be destructively removed. A second conductive layer is then provided on an exposed backside of the oxide layer. The addition of a second electrode on the second conductive layer yields the desired high quality capacitor. Further processing steps, such as solder bumping, may be carried out while the capacitor wafer is still attached to the handle wafer. When the desired processing steps are complete, the handle wafer is removed, and the relatively thin high quality integrated capacitor wafer results.