Integrated DFE Sampler Circuit for Low-Latency High-Speed I/O
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Solution Overview
Problem
High-speed I/O data circuits face performance issues due to distortion in the transmission channel, and existing solutions using analog front-end decision feedback equalizers contribute to power consumption, area occupancy, and latency.
Innovation Solution
Integration of decision feedback equalizer circuitry with sampler circuitry, eliminating the need for an analog front-end, and utilizing N latching samplers with equally spaced sample clocks and decision logic level thresholds to reduce power consumption, area, and latency, while enabling efficient data sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog front-end decision feedback equalizer is used, then equalization performance is improved, but power consumption increases
Solution Approach 1:
The patent merges the decision feedback equalizer (DFE) circuitry with the sampler circuitry into a single integrated structure. The DFE tap weights are generated and applied within the sampler block itself, eliminating the need for a separate analog front-end equalizer. This integration reduces the number of active components and interconnections, thereby reducing overall power consumption while maintaining equalization functionality.
Solution Approach 2:
The patent extracts the DFE functionality from the traditional analog front-end architecture and relocates it into the digital sampler domain. By taking out the separate equalizer block and embedding its functionality within the sampler, the design eliminates redundant circuitry and reduces power consumption associated with running a dedicated analog equalizer.
2Reliability
If an analog front-end decision feedback equalizer is used, then equalization performance is improved, but area occupancy increases
Solution Approach 1:
The patent combines the DFE equalizer circuitry with the sampler circuitry into a single integrated block. The tap weight generation, feedback path, and sampling functionality are merged into one unified structure, significantly reducing the total silicon area required compared to having separate analog front-end equalizer and sampler blocks.
Solution Approach 2:
The integrated sampler-DFE block performs multiple functions: it samples the incoming signal, generates DFE tap weights, applies feedback equalization, and outputs the equalized data. This multi-functional integration eliminates the need for separate dedicated equalizer circuitry, thereby reducing area occupancy.
3Reliability
If an analog front-end decision feedback equalizer is used, then equalization performance is improved, but feedback equalization signal latency increases
Solution Approach 1:
The patent merges the DFE feedback path with the sampler timing structure, allowing tap weights to be generated and applied within the same clock cycle or with minimal delay. The integrated architecture enables the feedback signal to circulate through the DFE taps and be applied to the sampler output with minimal additional latency compared to separate analog front-end implementations.
4Measurement precision
If N latching samplers with equally spaced sample clocks are used, then data sampling accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the sampling function into N separate latching samplers, each synchronized to an equally spaced phase of the sample clock. This segmentation allows each sampler to capture data at a specific phase point, improving sampling accuracy by reducing intersymbol interference. The segmented architecture is managed through systematic interconnections between samplers and DFE taps.
Solution Approach 2:
The patent implements dynamic phase rotation of the sample clocks across N samplers, where each sampler operates at a different phase offset. This dynamic time-division approach allows the system to process multiple data streams or achieve higher effective sampling rates while using a manageable number of physical sampler circuits, balancing accuracy requirements with device complexity.
Data Source
AI summary
A signal sampling system that includes N samplers is disclosed. Each sampler includes a data input having a decision logic level threshold, a plurality of offset control inputs, a plurality of offset magnitude inputs, an un-buffered output, and a buffered output. Each sampler further includes circuitry coupled between the inputs and outputs that is configured to cause a time delay from an input signal transition to an output signal transition such that, after an offset control input transitions from a first voltage to a second voltage, the decision logic level threshold changes in a time substantially less than one gate delay, and after the sample clock transitions from a first logic state to a second logic state, the un-buffered output transitions within a time substantially equal to one gate delay and the buffered output transitions within a time substantially equal to two gate delays.