Integrated Dielectric Stack for MRAM and Logic Capacitance Matching
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Solution Overview
Problem
The manufacturing of semiconductor devices requires additional processes to form different dielectric layers for memory and logic devices, increasing complexity and cost due to varying electrical capacitance requirements.
Innovation Solution
A method for manufacturing a semiconductor device involving the formation of multiple dielectric layers with varying dielectric constants, including low-k and high-k dielectric layers, to meet specific capacitance requirements, allowing for integration of dielectric layers for both memory and logic devices, thereby simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different dielectric layers are formed separately for memory and logic devices, then capacitance requirements are met, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the dielectric layer formation processes for memory and logic devices into a unified sequence. The first dielectric layer (low-k) and second dielectric layer (high-k) are formed in an integrated manner where the second dielectric layer is formed over the first dielectric layer, allowing both memory and logic devices to share common manufacturing steps while meeting their respective capacitance requirements
Solution Approach 2:
The first dielectric layer with low dielectric constant serves dual purposes: it provides electrical isolation for logic devices requiring low capacitance and serves as a base layer for memory devices requiring high capacitance. The second dielectric layer with high dielectric constant is selectively formed over the first dielectric layer to provide additional capacitance for memory devices, while the same first dielectric layer structure supports both device types
2Reliability
If additional processes are added to form different dielectric layers, then capacitance requirements are met, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple dielectric layer formation operations into a single integrated process flow. By forming the first dielectric layer across the entire substrate and then selectively forming the second dielectric layer in memory device regions, the manufacturing process reduces the total number of separate steps compared to forming dielectric layers independently for each device type
Solution Approach 2:
The first dielectric layer is formed in advance across the entire substrate before device-specific structures are fully defined. This preliminary formation of the low-k dielectric layer provides a common foundation that simplifies subsequent processing steps and reduces the need for additional preparatory processes for different device regions
3Reliability
If multiple dielectric layers with varying dielectric constants are formed, then capacitance requirements are met, but planarization is improved
Solution Approach 1:
The patent applies different dielectric constant properties to different spatial regions: the first dielectric layer with low dielectric constant (k<3.5) is formed across the entire substrate, while the second dielectric layer with high dielectric constant (k>3.5) is selectively formed only in memory device regions. This local differentiation allows each region to have optimized electrical properties while maintaining overall structural integrity and planarization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the semiconductor device to meet capacitance requirements for both memory and logic devices, reducing manufacturing complexity and cost by integrating dielectric layers, and improving planarization of the semiconductor device.
Implementation Method 1
a first dielectric layer, a second dielectric layer over the first dielectric layer... a dielectric constant of the second dielectric layer is higher than a dielectric constant of the first dielectric layer
Data Source
AI summary
A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.