Integrated Dipole Gate Stack for Vt Tuning Without EOT Penalty
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Solution Overview
Problem
Conventional methods face challenges in manufacturing transistors with reduced thickness, lower thermal budget, and multi-Vt requirements while maintaining precise control of dipole species in metal gate stacks, leading to issues like EOT penalty and device leakage.
Innovation Solution
A method involving the deposition of an interfacial layer, high-κ dielectric layer, and a dipole layer, such as a metal oxynitride layer, followed by a capping layer, using techniques like ALD, to form a transistor structure that allows for precise control of dipole species and reduces EOT penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional spike anneal is used to achieve dipole effect, then desired dipole effect is achieved, but EOT penalty and high thermal budget occur due to oxygen diffusion oxidizing underlying silicon
Solution Approach 1:
The patent applies preliminary action by depositing a protective capping layer (such as silicon nitride or silicon oxide) over the dipole layer before spike anneal. This capping layer prevents oxygen from the dipole layer from diffusing downward and oxidizing the underlying silicon channel, thereby eliminating EOT penalty while still allowing the dipole effect to be achieved during the anneal process.
Solution Approach 2:
The patent introduces a capping layer as an intermediary between the dipole layer and the silicon channel. This intermediary layer acts as a barrier to oxygen diffusion, preventing the harmful interaction between oxygen and silicon while allowing the dipole layer to maintain its desired electrical properties for Vt tuning.
2Manufacturing precision
If ALD process is used to deposit dipole layer, then precise thickness control is achieved, but film thickness cannot be reduced below 3 Å due to discontinuous growth
Solution Approach 1:
The patent applies parameter changes by modifying the deposition parameters of the ALD process, specifically using lower deposition temperatures and adjusted precursor dosing to achieve continuous film growth at thicknesses below the conventional 3 Å limit. This allows for precise thickness control down to 1-2 Å, enabling finer Vt tuning without discontinuous growth.
Solution Approach 2:
The patent applies local quality by creating dipole layers with non-uniform composition or thickness profiles. By varying the local properties of the dipole layer (such as oxygen content or thickness at different positions), the patent achieves precise Vt control while maintaining continuous film growth throughout the layer.
3Productivity
If device dimensions are shrunk to increase functional density, then more devices per chip area are achieved, but switching speeds and dimensional control become difficult
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar FET geometry to FinFET three-dimensional structure. This vertical dimension provides better electrostatic control over the channel, enabling precise dimensional control and switching characteristics even as device dimensions are shrunk to increase functional density on the chip.
Solution Approach 2:
The patent applies segmentation by dividing the gate structure into multiple segments (gate-all-around configuration) that wrap around the channel from multiple directions. This segmented approach provides superior control over the channel dimensions and electrical properties, maintaining manufacturing precision despite overall device scaling.
4Adaptability or versatility
If multi-Vt requirements are implemented, then different threshold voltages are achieved, but Vt tuning range is limited by film thickness variation
Solution Approach 1:
The patent applies composite materials by combining the dipole layer (for Vt tuning) with a high-k dielectric layer (for capacitance enhancement) and a capping layer (for protection). This composite gate stack structure enables broader Vt tuning range through the dipole layer while the high-k dielectric maintains strong electrostatic control, overcoming the limitation of film thickness variation.
Solution Approach 2:
The patent applies dynamics by making the Vt characteristic adjustable and dynamic through the dipole layer. By controlling the amount and distribution of dipole species (such as oxygen or nitrogen) in the dipole layer, the Vt can be dynamically tuned across a wide range, enabling multi-Vt devices with enhanced adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves improved Vt tuning without increasing EOT, enhancing device performance and reliability by embedding dipole species into the high-κ dielectric layer, thereby improving Vt without excess EOT penalty.
Implementation Method 1
depositing a dipole layer on the high-κ dielectric layer
Implementation Method 2
depositing a high-κ dielectric layer on the interfacial layer
Data Source
AI summary
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-k dielectric layer.