Integrated Egress Replay Memory for Head-of-Line Blocking
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Solution Overview
Problem
In multi-rate network systems, the head-of-line blocking problem and delayed nullification defect occur due to varying egress rates, leading to decreased network efficiency and delayed error notification, as slower packets hinder faster packets and error detection is delayed, affecting error handling and resource utilization.
Innovation Solution
An integrated egress/replay memory structure with split rate write and read ports manages egressing, replay, and to-be-egressed packet data, allowing high-speed entry of to-be-egressed data even when egressing data is slow, and quickly erasing storage areas for efficient data flow and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate buffers are used for egressing and replay data, then data integrity is maintained, but head-of-line blocking occurs and network efficiency decreases
Solution Approach 1:
The patent combines separate egressing data buffer and replay data buffer into a single integrated buffer structure. This unified buffer allows flexible allocation of storage space between egressing packets and replay packets, enabling faster packets to bypass slower ones without causing head-of-line blocking, while maintaining data integrity through proper buffer management protocols
2Productivity
If to-be-egressed data enters at high speed, then ingress efficiency is improved, but head-of-line blocking occurs when egress rate is slow
Solution Approach 1:
The patent segments the buffer into distinct regions for to-be-egressed data, egressing data, and replay data. The to-be-egressed data can be written at high speed into its designated region without being blocked by the egress rate of other packets. This segmentation allows independent flow control for different data stages, eliminating head-of-line blocking between ingress and egress operations
3Productivity
If error detection is performed after packet egress, then data transmission is completed, but error notification is delayed
Solution Approach 1:
The patent performs error detection and generates nullification flags during the egress process itself, before the packet fully leaves the system. When a nullification flag is generated for a packet, the corresponding buffer space can be immediately reclaimed and reused. This preliminary error detection mechanism eliminates delays in error notification and enables immediate resource reallocation, improving both error handling speed and buffer utilization efficiency
Data Source
AI summary
An integrated egress/replay memory structure is provided with split rate write and read ports and means for managing at least three types of data moving into, through and/or out of the integrated memory structure, namely: (1) currently egressing packet data; (2) replay data; and (3) to-be egressed data. Additionally, a shared free space (4) is managed between the storage areas of the (2) replay data and (3) the to-be egressed data. The to-be egressed data (PdBx) is allowed to enter into (to be written into) a front-end raceway portion of the integrated memory structure at a rate which can be substantially greater than that allowed for corresponding egressing packet data (PdUx). Thus, even when egressing packet data that is ahead in line is shifting out toward a slow rate egress port, this slowing factor does not slow the speed at which the to-be egressed data (PdBx) can be shifted into the front-end raceway portion. A shared free space memory area is maintained between the storage areas of the replay data (PdAx) and to-be-egressed data (PdBx). When a positive acknowledgement (ACK) is received from the destination of already-egressed data (of the After-Transmission Data, or PdAx), the corresponding replay storage area (the area storing the acknowledged PdAx data) can be reallocated for use as an empty part of the raceway portion.