Integrated Egress Replay Memory Structure for Packet Data
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Solution Overview
Problem
Networks with multi-rate systems face issues such as head-of-line blocking and delayed nullification notices due to varying egress flow rates, leading to inefficiencies and increased latency in data transmission.
Innovation Solution
An integrated egress/replay memory structure with split rate write and read ports manages egressing, replay, and to-be-egressed packet data, allowing for high-speed write-in of to-be-egressed data and efficient handling of acknowledged or nullified data to alleviate head-of-line blocking and expedite error notification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single memory structure is used for storing egressing packet data, replay data, and to-be-egressed data, then device complexity is reduced, but head-of-line blocking occurs and productivity decreases
Solution Approach 1:
The memory structure is segmented into distinct regions: a first memory region for storing to-be-egressed packet data and a second memory region for storing egressing packet data and replay data. This segmentation allows independent management of different data types, preventing head-of-line blocking where slow egressing data would block faster to-be-egressed data from being written.
Solution Approach 2:
A pointer mechanism acts as an intermediary to manage the boundary between the first and second memory regions. The pointer dynamically indicates the current boundary position, allowing the system to flexibly allocate memory space and switch between storing to-be-egressed data and egressing/replay data without physical memory movement or complex control logic.
2Device complexity
If egress data is stored at the same rate as write-in rate, then memory management is simplified, but slow egress ports bottleneck the flow of new data
Solution Approach 1:
The memory allocation between to-be-egressed data and egressing/replay data is dynamic rather than fixed. The pointer adjusts the boundary between memory regions based on current operational needs, allowing the system to allocate more memory space to to-be-egressed data when write-in speed is high, thereby preventing data loss without requiring complex rate-matching control.
Solution Approach 2:
The system prepares memory space in advance by maintaining a buffer region (first memory region) dedicated to storing to-be-egressed data at high speed. This preliminary preparation of storage space allows data to be written continuously without waiting for egress, eliminating the bottleneck effect of slow egress ports.
3Productivity
If separate memory structures are used for different data types, then head-of-line blocking is prevented, but device complexity increases
Solution Approach 1:
The patent merges the functionality of separate memory structures into a single integrated memory device that contains both the first memory region (for to-be-egressed data) and the second memory region (for egressing and replay data). This consolidation achieves the performance benefits of separate structures while reducing device complexity through physical integration and shared control logic.
4Reliability
If error notification is delayed until egress completion, then data integrity is ensured, but error notification latency increases
Solution Approach 1:
The system performs error checking on to-be-egressed data while it is still in the first memory region, before the data is transferred to the second memory region for egress. This preliminary error detection allows the system to identify and handle erroneous data early, reducing error notification latency without compromising data integrity, as the error can be detected and reported before the data consumes egress resources.
Data Source
AI summary
An integrated egress/replay memory structure is provided with split rate write and read ports and means for managing at least three types of data moving into, through and/or out of the integrated memory structure, namely: (1) currently egressing packet data; (2) replay data; and (3) to-be egressed data. Additionally, a shared free space (4) is managed between the storage areas of the (2) replay data and (3) the to-be egressed data. The to-be egressed data (PdBx) is allowed to enter into (to be written into) a front-end raceway portion of the integrated memory structure at a rate which can be substantially greater than that allowed for corresponding egressing packet data (PdUx). Thus, even when egressing packet data that is ahead in line is shifting out toward a slow rate egress port; this slowing factor does not slow the speed at which the to-be egressed data (PdBx) can be shifted into the front-end raceway portion. A shared free space memory area is maintained between the storage areas of the replay data (PdAx) and to-be-egressed data (PdBx). When a positive acknowledgement (ACK) is received from the destination of already-egressed data (of the After-Transmission Data, or PdAx), the corresponding replay storage area (the area storing the acknowledged PdAx data) can be reallocated for use as an empty part of the raceway portion.