Integrated Erase Voltage Path for Nonvolatile Memory Blocks
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Solution Overview
Problem
Existing flash memory devices face inefficiencies in cost, performance, and power consumption due to their erase schemes, which involve large charge pumps and can cause erase disturb in multi-level flash cells, leading to unintended changes in programmed threshold voltages.
Innovation Solution
A non-volatile memory device with at least two groups of memory cells and row circuitry that selectively provides an erase voltage to each group, integrating the erase voltage path with existing row decoding circuitry to minimize additional decoding logic and circuitry, and using pocket wells to isolate memory blocks and reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large charge pumps are used to provide erase voltage for memory blocks, then erase operation can be performed, but chip area increases and manufacturing cost increases
Solution Approach 1:
The patent divides the memory array into multiple independently erasable memory blocks, each with its own dedicated erase voltage path. This segmentation allows selective erasing of individual blocks without requiring a single large charge pump that serves all blocks, thereby reducing overall chip area while maintaining erase operation capability.
Solution Approach 2:
The patent implements local erase voltage generation and distribution for each memory block, providing tailored erase capability to specific regions. This local approach eliminates the need for a centralized large charge pump, reducing chip area while ensuring reliable erase operations in each block.
2Device complexity
If erase voltage is applied to all memory blocks simultaneously, then erase operation is simplified, but unselected blocks experience erase disturb causing unintended threshold voltage changes
Solution Approach 1:
The patent segments the erase voltage distribution into independent paths for each memory block, controlled by individual block select signals. This enables precise control where only selected blocks receive erase voltage, preventing erase disturb in unselected blocks while maintaining manageable control complexity through systematic signal distribution.
Solution Approach 2:
The patent introduces block select signals as intermediary control elements that gate the erase voltage to specific memory blocks. These intermediaries enable selective activation of erase paths, ensuring that only intended blocks undergo erasure while protecting unselected blocks from threshold voltage disturbances.
3Ease of manufacture
If multiple memory blocks are erased simultaneously using shared erase voltage path, then manufacturing cost is reduced, but erase speed decreases due to increased capacitance
Solution Approach 1:
The patent segments erase voltage paths into separate channels for different memory blocks, each with controlled impedance and capacitance. This allows parallel or sequential erasure of multiple blocks without the cumulative capacitance penalty of a shared path, maintaining faster erase speeds while using standardized circuit blocks that reduce manufacturing complexity.
Solution Approach 2:
The patent transitions from a single-plane shared erase voltage architecture to a multi-dimensional structure where erase paths are distributed across multiple independent channels. This dimensional reorganization enables simultaneous or rapid sequential erasure of multiple blocks, overcoming the capacitance bottleneck while maintaining manufacturing efficiency through modular design.
Data Source
AI summary
A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.