Integrated Error Sampler Circuit for Equalizer Timing Relaxation
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Solution Overview
Problem
Serial communication systems face challenges in channel equalization due to high frequency distortion, leading to inter-symbol interference, where existing solutions either complicate decision feedback equalizer timing or require precise delay matching, which is difficult to achieve.
Innovation Solution
An error sampler circuit with an integrated slicer that merges slicing and sampling, eliminating the need for additional slicers and degeneration resistors, allowing for higher gain and sensitivity while using the same clock signal for both data and error sampling, thus simplifying the decision feedback equalizer timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate slicer and sampling circuits are used in decision feedback equalizer, then slicing and sampling functions are performed, but device complexity increases and timing requirements become more stringent
Solution Approach 1:
The patent combines the slicer and sampling functions into a single integrated error sampler circuit. The differential input stage directly performs both comparison against reference voltage and sampling operations simultaneously, eliminating the need for separate slicer and sampler circuits. This merging reduces device complexity while maintaining equalization performance.
Solution Approach 2:
The error sampler circuit performs multiple functions: it acts as both a slicer (comparing signal to reference) and a sampler (capturing error values at specific timing), while also providing differential to single-ended conversion. This multi-functionality reduces the overall number of components needed in the decision feedback equalizer.
2Measurement precision
If additional slicers and degeneration resistors are used, then slicing accuracy is improved, but power consumption increases and gain is reduced
Solution Approach 1:
The patent removes the degeneration resistors from the traditional slicer configuration. By eliminating these resistive elements, the circuit achieves higher gain and lower power consumption while maintaining slicing accuracy through the differential input architecture that directly compares the signal to the reference voltage without resistive degradation.
Solution Approach 2:
The patent changes the operating parameters by using a differential input architecture that operates with higher impedance and lower power consumption. The differential pair configuration allows for higher gain operation compared to traditional single-ended slicers with degeneration resistors, achieving both precision and energy efficiency.
3Loss of time
If different clock signals are used for data and error sampling, then sampling timing can be optimized, but timing synchronization becomes more difficult
Solution Approach 1:
The patent merges the data sampling and error sampling operations into a single clocked process. Both sampling operations use the same clock signal, which simplifies timing synchronization while the internal circuitry ensures that both samples are taken at the appropriate phases of the clock cycle, maintaining timing precision.
Data Source
AI summary
An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.