Integrated Ethernet Controllers with Single Bus Interface

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Solution Overview

Problem

High-speed digital communication networks face challenges in managing increased data rates and bandwidth due to high device and pin counts, leading to interference and increased implementation costs, particularly in high-frequency applications where chip and PCB real estate is expensive.

Innovation Solution

A method and system that integrates multiple Ethernet controllers onto a single chip with a single bus interface, using a processor to determine and manage bus identifiers, device identifiers, and function identifiers to route messages efficiently, allowing for independent processing and data transfer between controllers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If multiple Ethernet controllers are integrated onto a single chip with a single bus interface, then chip real estate and implementation cost are reduced, but device complexity increases due to the need for identifier management and message routing

Engineering Contradiction:

Improvechip real estateVSAvoididentifier management complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

Multiple Ethernet controllers are merged onto a single chip sharing a common bus interface, reducing chip real estate and implementation cost. The controllers share identification resources (bus identifier and device identifier) while maintaining independent function identifiers, allowing efficient resource utilization without proportionally increasing complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The identification system is segmented into three distinct components: bus identifier (shared by all controllers on the bus), device identifier (shared by all controllers on the same chip), and function identifier (unique to each controller). This segmentation allows hierarchical resource sharing and reduces overall system complexity.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If multiple Ethernet controllers share a single bus interface, then implementation cost is reduced, but interference increases due to high device and pin counts

Engineering Contradiction:

Improveimplementation costVSAvoidinterference

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

Multiple Ethernet controllers are combined onto a single chip with a shared bus interface, reducing the total device count and pin count required. This merging approach lowers implementation cost and reduces interference by eliminating the need for separate high-frequency interfaces for each controller.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The single bus interface is designed to serve multiple Ethernet controllers simultaneously, making it a universal interface that handles communication with all controllers. This multi-functionality reduces the need for multiple dedicated interfaces, thereby reducing interference and implementation cost.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Area of stationary object

If multiple Ethernet controllers are integrated on a single chip, then real estate and cost are minimized, but message routing complexity increases

Engineering Contradiction:

Improvechip real estateVSAvoidmessage routing complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The message routing process is segmented into three sequential steps based on identifier matching: first matching the bus identifier to identify the target bus, then matching the device identifier to identify the target chip, and finally matching the function identifier to identify the specific controller. This segmentation simplifies the routing logic compared to using a single complex addressing scheme.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The identifier matching process is structured to perform preliminary actions in a hierarchical manner, filtering messages at each level (bus level, device level, function level) before reaching the final destination. This preliminary filtering reduces the complexity of message routing by eliminating unnecessary comparisons at each stage.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7644194B2Method and system for addressing a plurality of Ethernet controllers integrated into a single chip which utilizes a single bus interface

Publication Date: 2010.01.05 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

Certain embodiments of the invention may include receiving at least one message via a single bus interface to which each integrated Ethernet controller may be coupled. A bus identifier, bus device identifier and bus function identifier corresponding to the received message and which identifies a particular one of the integrated Ethernet controllers may be determined. The received message may be transferred to the particular integrated Ethernet controller based on the determined bus identifier, bus device identifier and bus function identifier, which were previously generated. The method may further include associating a bus function with the particular integrated Ethernet controller and mapping the associated bus function identifier to the bus function. A bus function process may be associated with the particular integrated Ethernet controller. The bus identifier may be associated with the single bus interface and the device identifier may be associated with the plurality of integrated Ethernet controllers.