Integrated FET Reducing Parasitic Impedance in Drive Path
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Solution Overview
Problem
Parasitic impedances in the drive path of discrete Field Effect Transistors (FETs) lead to slow switching, high switching losses, low efficiency, and electromagnetic interference, causing noise sensitivity and potential unintended FET turn-on issues.
Innovation Solution
Integration of a power FET and a pull-down FET on the same die using a shared mask set and process steps, with distinct drain and source stripes and gate regions to reduce parasitic impedance, and forming a substrate with buried layers to isolate these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If discrete FET with independent gate driver is used, then switching operation can be controlled, but parasitic impedance in drive path causes slow switching and high switching loss
Solution Approach 1:
The patent merges the power FET and pull-down FET into a single integrated device structure, eliminating the external drive path and its parasitic impedance. The gate terminal is directly connected to the power FET gate, removing the parasitic resistance and inductance that would otherwise slow switching and increase losses.
Solution Approach 2:
The pull-down FET acts as an intermediary element that actively pulls the gate voltage to ground during turn-off, compensating for the effects of parasitic impedance in the drive path and ensuring fast, clean switching transitions without unintended turn-on.
2Object-affected harmful factors
If discrete FET with independent gate driver is used, then gate control is achieved, but parasitic impedance generates EMI and noise
Solution Approach 1:
By integrating the pull-down FET with the power FET in a single device, the patent eliminates the external drive path that generates EMI and noise. All control signals remain internal to the device package, significantly reducing electromagnetic interference and noise sensitivity.
3Device complexity
If discrete FET with independent gate driver is used, then switching control is possible, but device complexity increases
Solution Approach 1:
The patent combines two FET functions (power switching and gate pull-down) into a single integrated device, reducing the number of external components and connections. This simplification reduces the overall system complexity while improving reliability by eliminating external parasitic elements and potential failure points.
Data Source
AI summary
A FET device has a substrate, a plurality of repetitive source stripes, a first layout of drain stripe having a first drift region and a first drain region, a second layout of drain stripe having a second drift region and a second drain region, a first drain contactor contacted with the first drain region and connected to a drain terminal, a second drain contactor contacted with the second drain region and connected to a first gate terminal, a source contactor contacted with a source region in each of the plurality of repetitive source stripes and connected to a source terminal, a first gate region positioned between the source region and the first drain region and connected to the first gate terminal, and a second gate region positioned between the source region and the second drain region and connected to a second gate terminal.