Integrated Circuit Fin Structure Layout for Fixed Cell Area
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Solution Overview
Problem
Existing integrated circuit (IC) manufacturing methods do not effectively utilize varying numbers of fins in FinFETs, limiting the driving ability of IC devices and requiring increased cell area for higher performance.
Innovation Solution
The method involves generating an IC layout diagram that positions FinFETs with differing numbers of fins, allowing for increased driving ability without expanding the cell area by using fin track arrangements that support placement of cells with varying fin counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FinFETs with varying numbers of fins are used to increase driving ability, then the driving ability of IC devices is improved, but the cell area must be increased to accommodate the additional fins
Solution Approach 1:
The patent utilizes the vertical dimension by forming fins that extend perpendicular to the substrate surface. This allows multiple fins to be stacked vertically within the same planar cell area, thereby increasing the total fin count and driving ability without expanding the cell's footprint area. The fins are formed in a third dimension (vertical height) rather than requiring additional horizontal space.
Solution Approach 2:
The patent divides the active region into multiple discrete fin structures (e.g., first plurality of fins and second plurality of fins) that can be independently positioned and configured. This segmentation allows different regions of the cell to have different numbers of fins based on local performance requirements, optimizing the balance between driving ability and area utilization without requiring uniform expansion of the entire cell.
2Power
If the cell area is increased to accommodate more fins, then the driving ability is improved, but the integration density of the IC device is reduced
Solution Approach 1:
By transitioning from a two-dimensional planar arrangement to a three-dimensional vertical fin structure, the patent achieves higher integration density. Multiple fins are packed vertically within the same cell footprint, allowing more transistors to be integrated into the same area, thereby improving both driving ability and integration density simultaneously rather than trading one for the other.
Solution Approach 2:
The patent implements non-uniform fin distributions where different regions of the cell have different numbers of fins based on local circuit requirements. This allows critical regions to have higher fin counts for enhanced driving ability while other regions maintain minimal fin counts, optimizing the overall integration density without requiring uniform area expansion.
3Power
If FinFETs with different numbers of fins are positioned in the cell, then the driving ability is enhanced, but the manufacturing complexity increases due to varying fin configurations
Solution Approach 1:
The patent segments the fin formation process into distinct, manageable steps using separate photolithography and etching operations. By dividing the complex task of creating varying fin configurations into modular process segments, the patent reduces manufacturing complexity while still achieving the desired variation in fin counts for optimized driving ability in different circuit regions.
Data Source
AI summary
A method of manufacturing an integrated circuit (IC) device includes constructing a first row of fin field-effect transistors (FinFETs) by forming a first total number of one of n-type fins or p-type fins, constructing a second row of FinFETs adjacent to the first row of FinFETs by forming a second total number of the one of the n-type fins or the p-type fins, and constructing a third row of FinFETs adjacent to the second row of FinFETs by forming the first total number of the other of the n-type fins or the p-type fins, wherein the second total number of fins is one greater or one fewer than the first total number of fins.