Integrated Half-Bridge GaN Driver to Cut Switching Inductance
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Solution Overview
Problem
Existing half-bridge driver designs using GaN FETs face challenges with high gate and common source inductances, which lead to increased switching node parasitics and power losses.
Innovation Solution
The integration of a GaN FET with its driver in a packaged IC, allowing the IC to function as both a low-side and high-side switch without an external level-shifter or boot-strap circuit, and positioning signal and supply pins to minimize routing space and reduce inductances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If GaN FET is integrated with driver in packaged IC, then gate and common source inductances are reduced, but device complexity increases
Solution Approach 1:
The patent integrates the GaN FET power switch and gate driver circuitry into a single packaged IC, merging previously separate components. This integration reduces gate and common source inductances by minimizing the physical distance between the driver output and the FET gate terminal, thereby reducing power losses during switching operations.
Solution Approach 2:
The integrated IC is designed to function as both a low-side and high-side switch in half-bridge configurations, eliminating the need for separate external level-shifter or boot-strap circuits. This multi-functionality reduces the overall system component count while maintaining the power loss benefits of integration.
2Adaptability or versatility
If external level-shifter and boot-strap circuit are used, then high-side switching is enabled, but device complexity and routing space increase
Solution Approach 1:
The gate driver circuit within the integrated IC is designed with inherent high-side switching capability, eliminating the need for external level-shifter or boot-strap circuits. The driver can directly generate the necessary gate drive voltages for both low-side and high-side GaN FET configurations, providing universal adaptability while reducing system complexity.
3Loss of energy
If signal and supply pins are positioned to minimize routing space, then inductances are reduced, but manufacturing precision requirements increase
Solution Approach 1:
By integrating the driver and FET in the same package, the critical signal routing between them is minimized to internal traces rather than external PCB traces. This merging of components inherently reduces the routing space and associated inductances, while the internal routing is manufactured with controlled precision during the IC fabrication process.
Data Source
AI summary
An integrated circuit is provided which comprises a transistor and a driver coupled to a gate of the transistor. In at least one example, the driver controls an operation of the transistor, wherein the driver is operable in a first configuration as a low-side gate driver for a voltage regulator, and wherein the transistor is operable in the first configuration as a low-side switch for the voltage regulator. In at least one example, the driver is operable in a second configuration as a high-side gate driver for the voltage regulator, and wherein the transistor is operable in the second configuration as a high-side switch for the voltage regulator.