Integrated Gate Contact Structure for Low-Capacitance 3D Semiconductors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing aspect ratio and reduced contact-poly-pitch in 3D-stacked semiconductor devices lead to challenges in yield improvement due to short-circuit risks and capacitance increases between gate contact structures and other circuit elements.
Innovation Solution
A semiconductor device design where the gate contact structure is integrated as a portion of the gate structure itself, eliminating the need for a separate connection surface or interface, and featuring a protrusion or pillar on the gate structure to facilitate signal reception.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate gate contact structure is formed on the gate structure, then the gate input signal can be received, but the aspect ratio increases and short-circuit risk increases
Solution Approach 1:
The gate contact structure is merged with the gate structure by forming the gate contact structure as a portion of the gate structure itself, eliminating the need for a separate connection surface or interface. This integration reduces the overall height and aspect ratio while minimizing short-circuit risks between the gate contact structure and other circuit elements.
2Reliability
If a separate gate contact structure is formed on the gate structure, then the gate input signal can be received, but capacitance increases between gate contact structure and other circuit elements
Solution Approach 1:
The gate contact structure is merged with the gate structure, reducing the number of separate components and interfaces. This integration decreases the capacitance between the gate contact structure and other circuit elements while simplifying the overall device structure.
3Reliability
If a connection surface or interface is formed between gate contact structure and gate structure, then signal transmission is enabled, but misalignment risk increases
Solution Approach 1:
The gate contact structure and gate structure are merged into a single integrated structure, eliminating the connection surface or interface that would require precise alignment. This integration removes misalignment risks and simplifies the manufacturing process by reducing the number of patterning and alignment steps.
Data Source
AI summary
Provided is a semiconductor device which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate structure.