Integrated Gate Driver Clock Line and Passivation for LCD Bezel
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Solution Overview
Problem
In liquid crystal display (LCD) devices, the presence of external clock lines outside the gate driver limits the ability to achieve a narrow bezel and slim design, and the integration of a gate driver in the array substrate is prone to moisture penetration, leading to potential deterioration under high humidity conditions.
Innovation Solution
An array substrate with an integrated gate driver is designed, where the conductive pattern functions as both clock lines and jumping lines, formed over the gate driver, and a second passivation layer is used to prevent moisture ingress, reducing the bezel area and enhancing durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If external clock lines are disposed outside the gate driver, then the gate driver can be properly connected to clock signals, but the bezel area increases and the device cannot achieve a slim profile
Solution Approach 1:
The patent merges the clock line function with the gate driver structure by integrating clock lines inside the gate driver region. The conductive patterns serving as clock lines are formed within the gate driver area, eliminating the need for separate external clock line routing and thereby reducing the bezel area while maintaining proper clock signal connection to the gate driver.
Solution Approach 2:
The patent utilizes vertical stacking in the film structure to accommodate clock lines within the gate driver region. By forming conductive patterns at different layers (gate electrode layer, source/drain electrode layer, pixel electrode layer) and using insulating layers for separation, the clock lines are integrated in the vertical dimension rather than requiring additional horizontal space, thus reducing bezel area.
2Weight of stationary object
If the gate driver is integrated in the array substrate, then the device volume and weight are reduced, but moisture penetration causes deterioration under high humidity conditions
Solution Approach 1:
The patent employs multiple insulating film layers (gate insulating layer, interlayer insulating layer, passivation layer) that form a protective barrier over the integrated gate driver structures. These thin film layers encapsulate the conductive patterns and gate driver components, preventing moisture penetration while maintaining the compact integrated design, thus improving reliability without sacrificing weight reduction benefits.
Solution Approach 2:
The patent uses composite multi-layer structures combining different materials (conductive materials for electrodes, insulating materials for gate insulating layer and passivation layer, transparent insulating materials for interlayer insulating layer) to create a protected integrated gate driver system. This composite structure provides both the integrated functionality for weight reduction and moisture barrier properties for reliability.
3Length of stationary object
If the gate driver is integrated in the array substrate, then the device thickness is reduced, but moisture penetration causes deterioration under high humidity conditions
Solution Approach 1:
The patent employs multiple insulating film layers (gate insulating layer, interlayer insulating layer, passivation layer) that form a protective barrier over the integrated gate driver structures. These thin film layers encapsulate the conductive patterns and gate driver components, preventing moisture penetration while maintaining the compact integrated design, thus improving reliability without sacrificing thickness reduction benefits.
Solution Approach 2:
The patent uses composite multi-layer structures combining different materials (conductive materials for electrodes, insulating materials for gate insulating layer and passivation layer, transparent insulating materials for interlayer insulating layer) to create a protected integrated gate driver system. This composite structure provides both the integrated functionality for thickness reduction and moisture barrier properties for reliability.
Data Source
AI summary
An array substrate includes: a substrate; a gate connecting line on the substrate in a gate circuit area; a gate insulating layer on the gate connecting line; an active pattern on the gate insulating layer; a source connecting line and a pixel pattern sequentially disposed on the active pattern; an interlayer insulating layer and an organic pattern sequentially disposed on the gate insulating layer; a first passivation layer on the organic pattern; and a conductive pattern on the first passivation layer, the conductive pattern coupled to the gate connecting line and to the pixel pattern.