Integrated Gate Driver Layout for Display Panel Peripheral Area
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Solution Overview
Problem
Existing display devices with integrated gate drivers face limitations in design flexibility and area reduction of the peripheral area, as the gate driver and data driver are typically mounted on a printed circuit board or directly on the display panel, restricting the freedom in designing the peripheral area and increasing the area usage.
Innovation Solution
A display device design where the gate driver is integrated on the display panel, with stages and pixel rows arranged in a specific pattern, including a fan-out region with non-parallel gate lines and varying widths, allowing for misalignment and alignment of stages and pixel rows, and incorporating dummy stages and pixels to optimize space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate driver is mounted on a printed circuit board or directly on the display panel as a separate chip, then the connection and signal transfer are simplified, but the design flexibility of the peripheral area is restricted and the area usage increases
Solution Approach 1:
The gate driver is integrated directly on the display panel by forming transistor stages and capacitors using the same thin film transistor fabrication process as the pixel electrodes. This merging of the gate driver with the display panel eliminates the need for separate chips or PCB mounting, thereby improving design flexibility while maintaining manufacturing simplicity through process integration
2Adaptability or versatility
If the gate driver is integrated on the display panel, then the design flexibility of the peripheral area is improved, but the area of the peripheral region increases
Solution Approach 1:
The gate lines are configured to extend in directions that are not parallel to the first direction (row direction) and not parallel to the second direction (column direction), creating diagonal or angled routing paths. This dimensional change in gate line orientation allows for more efficient space utilization in the peripheral area, reducing the overall area required while maintaining design flexibility
3Ease of manufacture
If the stages and pixel rows are aligned in a regular pattern, then the manufacturing process is simplified, but the area usage efficiency is reduced
Solution Approach 1:
The gate lines are designed with asymmetric routing where at least one gate line extends in a direction that is not parallel to the first or second direction, creating irregular angular relationships between gate lines and pixel rows. This asymmetric configuration optimizes space utilization in the peripheral area while the transistor stages remain systematically formed through standardized fabrication processes
Data Source
AI summary
A display device includes: a display panel including a display area, and a peripheral area disposed in the vicinity of the display area; a scan driver including a plurality of stages integrated on the peripheral area; a plurality of gate lines connected to the plurality of stages, respectively; and a plurality of pixel rows in the display area and connected with the plurality of gate lines, respectively. The plurality of stages and the plurality of pixel rows are each arranged in a first direction in a line, the peripheral area includes a fan-out region between the plurality of stages and the plurality of pixel rows, and at least one of the plurality of gate lines in the fan-out region is inclined with respect to the first direction, and a second direction perpendicular to the first direction.