Integrated Gate Driving Circuit Reduces Bezel Size
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Solution Overview
Problem
Conventional gate driving circuits for display devices require separate scan drivers, leading to an increased bezel size due to the need for distinct drivers for first and second scan signals, which hampers the reduction of non-display areas and enhances user immersion by minimizing bezel size.
Innovation Solution
Integration of a first scan signal generator and a second scan signal generator using nodes Q/QB of a logic circuit, allowing for shared resources and optimized clock signal utilization to reduce bezel size and secure sufficient initialization time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate scan drivers are provided for first and second scan signals, then the driving function is reliable, but the bezel size increases
Solution Approach 1:
The patent merges the first scan driver and second scan driver into a single integrated scan driver. The first scan signal generator and second scan signal generator share common circuit components and output nodes, reducing the overall driver area while maintaining separate signal generation capabilities. This combining approach directly reduces the bezel size without sacrificing driving reliability.
Solution Approach 2:
The integrated scan driver performs multiple functions: it generates both the first scan signal (SC1) for data voltage transfer and the second scan signal (SC2) for compensation, using a unified circuit structure. The shared nodes Q/QB and common transistor components enable the single driver to fulfill the roles previously requiring separate drivers, achieving multi-functionality with reduced area.
2Stability of the object's composition
If separate scan drivers are used, then the scan signals are stable, but the device area increases
Solution Approach 1:
The patent combines the two scan drivers into one integrated unit that generates both SC1 and SC2 signals. The shared circuit components and nodes maintain signal stability through coordinated operation, while the reduced device area is achieved by eliminating redundant separate driver structures.
3Area of stationary object
If the gate driving circuit area is reduced, then the bezel size decreases, but the initialization time may be insufficient
Solution Approach 1:
The integrated scan driver is designed to provide sufficient initialization time (4 horizontal periods) before the sampling operation begins. The circuit timing is预先 arranged to ensure that the first scan signal generator has adequate time to initialize the driving transistor, preventing time loss despite the reduced driver area.
Solution Approach 2:
The patent uses dynamic clock signal phases (6-phase or 8-phase) to coordinate the operation of the integrated scan driver. The clock signals dynamically control the timing of signal generation and transmission, ensuring that initialization is completed within the available time frame while maintaining reduced bezel size.
Data Source
AI summary
A display device according to the present disclosure comprises a substrate including a display area and a non-display area, pixel circuits each including at least one n-type transistor and at least one p-type transistor and arranged in the display area, and a gate driving circuit included in the non-display area and outputting a first scan signal for applying a data voltage to driving transistors of the pixel circuits for an initialization time and a second scan signal that represents a same logic voltage as the first scan signal for the initialization time and represents a logic voltage reverse to the first scan signal for a sampling time. A first scan signal generator and a second scan signal generator are integrated using nodes Q/QB of a logic circuit to reduce a bezel size.