Integrated Memory, HV, and Logic Gate Fabrication Without Process Interference
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Solution Overview
Problem
Existing methods for forming semiconductor devices with memory cells, high voltage devices, and logic devices on the same substrate face challenges in processing steps that adversely affect concurrently fabricated devices.
Innovation Solution
A method involving a substrate with distinct areas for memory cells, high voltage devices, and logic devices, where specific recessing, insulation layer thinning, and conductive layer formation techniques are used to create separate and independent processing steps for each device type, ensuring minimal interference during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processing steps are used to form memory cells, high voltage devices and logic devices on the same substrate, then device integration is improved, but processing steps adversely affect concurrently fabricated devices
Solution Approach 1:
The substrate is divided into distinct regions (first area for memory cells, second area for high voltage devices, third area for logic devices) with different insulation layer thicknesses in each region, allowing independent processing optimization for each device type while maintaining integration on a single substrate
Solution Approach 2:
The insulation layer is formed with non-uniform thickness where the thickness in the third area (logic devices) is less than the thickness in the first and second areas (memory cells and high voltage devices), enabling different processing conditions and parameters to be applied locally to each device region to prevent mutual interference
2Reliability
If separate processing steps are used for each device type, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
A single insulation layer structure serves multiple functions: it provides electrical isolation for memory cells in the first area, high voltage isolation in the second area, and enables logic device processing in the third area through selective thinning, thereby reducing the need for separate processing steps for each device type
Data Source
Figure 1A~1C
Figure 2A~2C
Figure 3A~3C
AI summary
A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.