Integrated Gate Field Plate Transistor for Reduced Die Area

The patent combines the control terminal and field plate into a single integrated conductive structure. This structure includes a gate region that serves as the control terminal and a field plate region that extends from the gate, both formed as one continuous conductive element. This merging eliminates the need for separate control terminals and field plates while maintaining the electrical field control functionality, thereby reducing device complexity and area occupancy while preserving breakdown voltage characteristics.

The integrated conductive structure performs multiple functions simultaneously: it acts as both a control terminal for regulating current flow through the channel and as a field plate for controlling the electric field distribution in the extended drain region. This multi-functionality allows a single structure to replace what would traditionally require separate components, reducing overall device complexity while maintaining optimal breakdown voltage performance.

By merging the control terminal and field plate into a single integrated conductive structure, the patent reduces the total die area required. The field plate extends laterally from the gate region and is formed as one continuous structure, eliminating the need for separate control terminals and reducing overall area occupancy while maintaining effective electrical field control across the extended drain region.

The field plate extends in the lateral dimension from the gate region, allowing electrical field control to be achieved through spatial extension rather than requiring additional vertical stacking or separate lateral components. This dimensional approach enables effective field control while minimizing the footprint area occupied by the device structures.

The device is segmented into distinct functional regions: a vertical channel region for current flow, an extended drain region with drift region for voltage handling, and an integrated conductive structure with gate and field plate regions for control. This segmentation allows each region to be optimized independently while maintaining compatibility with standard semiconductor manufacturing processes, balancing area reduction with manufacturability.

The patent employs parameter changes in the doping concentrations and geometrical dimensions of various regions to optimize device performance. By adjusting doping levels in the extended drain region and channel region, and by controlling the dimensions of the vertical channel and field plate extension, the device achieves optimal breakdown voltage and electrical characteristics while remaining compatible with existing manufacturing capabilities.