Integrated Gate Resistor for HFET Switching Control
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Solution Overview
Problem
Conventional semiconductor devices for switched mode power converters face challenges in integrating a gate resistor without additional die area, which affects the dynamic control of switching speed, especially at high frequency operations.
Innovation Solution
A monolithic integrated gate resistor is incorporated into the HFET device chip, allowing for dynamic control of switching speed without requiring additional area, by positioning the gate resistor underneath the gate bus and array of gates, thereby integrating it with the HFET on the same die without increasing the die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a gate resistor is integrated into the HFET device chip, then switching speed control and oscillation damping are improved, but die area increases
Solution Approach 1:
The gate resistor is merged with the gate bus structure by forming the resistor within the same conductive layer that forms the gate bus. This integration allows the resistor to be part of the existing gate interconnect structure, eliminating the need for separate resistor structures and additional die area while maintaining the ability to control switching speed and damp oscillations.
Solution Approach 2:
The gate resistor is nested within the gate bus structure by positioning the resistor underneath the gate bus and array of gates. This nesting approach allows the resistor to occupy space that would otherwise be unused or partially used, effectively integrating the resistor function without increasing the overall die footprint.
2Reliability
If a gate resistor is added to damp oscillations, then circuit stability is improved, but device complexity increases
Solution Approach 1:
The gate resistor is combined with the existing gate bus conductive structure, eliminating the need for separate resistor components, additional fabrication steps, and complex interconnections. This merging approach maintains circuit stability while avoiding the complexity that would arise from adding a discrete resistor component.
3Area of stationary object
If the gate resistor is positioned underneath the gate bus, then die area is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The gate resistor and gate bus are formed as part of the same conductive structure in the same fabrication step, ensuring automatic alignment and eliminating the need for separate positioning operations. This merging approach minimizes die area while avoiding the manufacturing precision issues that would arise from attempting to position separate resistor and bus structures relative to each other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables effective damping of oscillations caused by low gate charge and capacitance, allowing for faster switching speeds and improved performance at elevated temperatures, while maintaining the compact size of the semiconductor device.
Implementation Method 1
effective damping of oscillations caused by low gate charge and capacitance
Data Source
AI summary
A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.