Integrated Gate Resistor for Oscillation Control in Semiconductor Devices

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Solution Overview

Problem

Semiconductor devices face destruction or adverse electromagnetic interference due to high voltage peaks and oscillations during switching processes, which existing solutions attempt to address with increased complexity and additional chip area, often requiring external gate resistance.

Innovation Solution

Integration of a conductive resistor layer with a grid-like pattern of openings in the gate pad region of semiconductor devices, forming an integrated gate resistor that provides a distributed resistance element, reducing oscillations and improving switching performance without increasing device size or complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If external gate resistance is used to reduce oscillations, then oscillations are reduced, but device complexity increases

Engineering Contradiction:
Improveoscillation reductionVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate resistor is merged with the gate electrode structure itself, forming an integrated gate connection. The gate electrode includes a first portion forming the gate and a second portion forming the gate resistor, both made from the same conductive material in a continuous structure. This eliminates the need for separate external gate resistance components while maintaining oscillation reduction functionality.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If additional capacitances are added to limit voltage and current rates, then switching performance is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveswitching performanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The gate resistor is integrated directly into the gate electrode structure during the same manufacturing process steps. The conductive material is deposited continuously to form both the gate electrode and gate resistor portions, eliminating the need for separate manufacturing processes for additional components.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If external components are added to reduce voltage peaks, then device reliability is improved, but chip area increases

Engineering Contradiction:
Improvedevice reliabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The gate resistor is formed as part of the gate electrode structure within the existing gate pad region. The second portion of the gate electrode extends into the gate pad region and provides the resistive function without requiring additional chip area beyond what is already allocated for gate connections.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The integrated gate resistor effectively reduces oscillations and enhances switching performance by providing a homogeneous voltage distribution and increased resistance, thus preventing device destruction and improving reliability while maintaining a compact design.

Implementation Method 1

Integration of a conductive resistor layer with a grid-like pattern of openings in the gate pad region of semiconductor devices, forming an integrated gate resistor that provides a distributed resistance element

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS8324686B2Semiconductor device and method for manufacturing
Publication Date: 2012.12.04 INFINEON TECH AUSTRIA AG
  • US8324686B2 patent drawing
  • US8324686B2 patent drawing
  • US8324686B2 patent drawing

AI summary

A semiconductor device and method for manufacturing. One embodiment provides a semiconductor device including an active cell region and a gate pad region. A conductive gate layer is arranged in the active cell region and a conductive resistor layer is arranged in the gate pad region. The resistor layer includes a resistor region which includes a grid-like pattern of openings formed in the resistor layer. A gate pad metallization is arranged at least partially above the resistor layer and in electrical contact with the resistor layer. An electrical connection is formed between the gate layer and the gate pad metallization, wherein the electrical connection includes the resistor region.