Integrated Gating Structure for GIDL Hole Generation
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Solution Overview
Problem
Conventional gating structures for select devices in NAND flash memory face difficulties in efficiently generating hole carriers for block-erase operations, and their utilization in other devices is limited.
Innovation Solution
Development of new gating structures with a common and continuous material forming a gating region and interconnecting region, suitable for select devices and other applications, which include a semiconductor channel material with a boundary region and a conductive material replacing replaceable structures to ensure consistent performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional gating structures are used for select devices, then device fabrication follows traditional processes, but the efficiency of generating hole carriers for block-erase operations is insufficient
Solution Approach 1:
The gating structure is divided into multiple segments including a first gating structure with a first gate electrode, a second gating structure with a second gate electrode, and intermediate structures. This segmentation allows each segment to contribute to hole carrier generation at different locations, improving overall efficiency while maintaining manageable complexity through modular design
Solution Approach 2:
The patent introduces vertical stacking of multiple gating structures at different heights, transitioning from a planar to a three-dimensional arrangement. This dimensional change enables simultaneous generation of hole carriers at multiple vertical positions, significantly improving block-erase efficiency without requiring a single overly complex structure
2Adaptability or versatility
If conventional gating structures are used, then fabrication processes are straightforward, but the structures cannot be effectively utilized in other device applications
Solution Approach 1:
The gating structure design incorporates universal features that enable its application in multiple device types beyond select devices. The modular architecture with standardized components (gate electrodes, dielectric layers, spacer formations) allows the same fabrication processes to be applied to different device configurations, achieving versatility without proportionally increasing manufacturing complexity
Solution Approach 2:
The gating structure employs dynamic elements such as adjustable spacer thicknesses and flexible material selections that can be tuned for different applications. This dynamic design allows the same basic structure to be adapted for various device requirements while maintaining a consistent fabrication workflow
3Manufacturing precision
If replaceable material structures are used in gating structures, then fabrication flexibility is improved, but performance consistency across devices is compromised
Solution Approach 1:
The patent carefully controls critical parameters such as spacer thickness, gate electrode dimensions, and material composition to ensure performance consistency. By establishing precise parameter specifications and control methods, the invention achieves reliable device performance while maintaining fabrication flexibility through parameter optimization rather than rigid structural constraints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new gating structures enable efficient generation of gate-induced drain leakage for block-erase operations and maintain consistent performance across devices, overcoming the limitations of conventional structures.
Implementation Method 1
A gating structure of a transistor may be utilized to provide gate-induced drain leakage (GIDL) which generates the holes utilized for block-erase of the memory cells
Data Source
AI summary
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.