Integrated GOA Circuit Unit for Narrow Frame Displays
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Solution Overview
Problem
Conventional gate driver on array (GOA) circuits require multiple TFTs and capacitors, leading to a wide frame design and potential output misalignment due to independent scan and emission circuit portions.
Innovation Solution
The GOA circuit unit integrates the scan and emission portions with a reduced number of TFTs and capacitors by using P-type TFTs and capacitors to generate scan signals from emission signals, allowing the output of the scan portion to be driven by the emission portion, thereby eliminating the need for additional TFTs and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two independent circuit portions (scan circuit and emission circuit) are used in conventional GOA circuits, then the functionality of generating scan signals and emission signals is achieved, but the number of TFTs and capacitors increases, leading to a wide frame design and potential output misalignment
Solution Approach 1:
The patent merges the scan circuit portion and emission circuit portion into an integrated GOA circuit unit. The emission circuit generates both emission signals and scan signals through shared components. Specifically, the emission circuit includes TFTs (T7-T16) and capacitors (C2-C4) that work together to generate emission signals while also producing scan signals through the interaction of these components, eliminating the need for separate independent scan and emission circuit portions.
Solution Approach 2:
The emission circuit portion is designed to perform multiple functions: generating emission signals for OLED control and simultaneously generating scan signals for pixel scanning. The TFTs and capacitors in the emission circuit serve dual purposes, with the output of the emission circuit driving both the emission function and the scan function through shared signal paths and components.
2Ease of operation
If two independent circuit portions are used in conventional GOA circuits, then scan signals and emission signals can be generated independently, but the frame width increases and narrow frame design cannot be achieved
Solution Approach 1:
The patent merges the scan circuit portion and emission circuit portion into an integrated GOA circuit unit. The emission circuit generates both emission signals and scan signals through shared components. Specifically, the emission circuit includes TFTs (T7-T16) and capacitors (C2-C4) that work together to generate emission signals while also producing scan signals through the interaction of these components, eliminating the need for separate independent scan and emission circuit portions.
3Ease of manufacture
If two independent circuit portions are used in conventional GOA circuits, then each circuit can be designed independently, but output misalignment occurs between scan signals and emission signals
Solution Approach 1:
The patent merges the scan circuit portion and emission circuit portion into an integrated GOA circuit unit. The emission circuit generates both emission signals and scan signals through shared components. Specifically, the emission circuit includes TFTs (T7-T16) and capacitors (C2-C4) that work together to generate emission signals while also producing scan signals through the interaction of these components, eliminating the need for separate independent scan and emission circuit portions.
Data Source
AI summary
A gate driver on array (GOA) circuit unit, including: a scan portion and an emission portion. The scan portion includes: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a first capacitor, a turn-on signal end, a first clock signal end, a second clock signal end, a power supply end, and a first node. The emission includes: a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, an eleventh TFT, a twelfth TFT, a thirteenth TFT, a fourteenth TFT, a fifteenth TFT, a sixteenth TFT, a second capacitor, a third capacitor, a fourth capacitor, a third clock signal end, a first controlling clock signal end, a second node, a third node, a fourth node, and a fifth node.


