Integrated Half-Bridge Semiconductor Packaging for Parasitic Inductance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor power supply systems face challenges in minimizing switching loss and parasitic effects due to parasitic inductance and impedance, which affect the safety and efficiency of power conversion.
Innovation Solution
A semiconductor packaging structure and power device design that integrates upper and lower tubes of the bridge arm switch inside the chip, eliminating the need for external connections and minimizing the size of the power switches, thereby reducing the impact of parasitic inductance and resistance, and allows the power electrode and ground terminal to be routed from the same side for easier capacitor placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If switching speed is increased to decrease switching loss, then switching loss is reduced, but peak voltage increases due to parasitic inductance threatening element safety
Solution Approach 1:
The patent merges the upper and lower tube power switches into a single integrated chip package, creating a half-bridge circuit module. This integration reduces the loop area between switches and minimizes parasitic inductance, allowing faster switching speeds without excessive voltage spikes that would threaten element safety.
Solution Approach 2:
The patent routes the power electrode and ground terminal from the same side of the chip, creating a planar layout that minimizes the vertical height of the current loop. This dimensional optimization reduces parasitic inductance and allows high-speed switching while maintaining element safety through reduced voltage overshoot.
2Loss of energy
If parasitic inductance and impedance are minimized by reducing loop size, then switching loss decreases, but device complexity increases due to integrated packaging requirements
Solution Approach 1:
The patent combines multiple power switches (upper and lower tubes) into a single integrated chip package with shared terminals. This merging reduces the overall loop area and parasitic inductance, decreasing switching loss while the standardized half-bridge packaging maintains reasonable device complexity through modular design.
3Loss of energy
If power switches are miniaturized to reduce parasitic effects, then switching loss is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent integrates multiple power switches onto a single chip with shared power and ground terminals. This consolidation minimizes the loop area and parasitic inductance, reducing switching loss. The manufacturing precision challenges are addressed through standard semiconductor fabrication processes that routinely achieve the required dimensional tolerances for integrated power devices.
Data Source
AI summary
A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.