Integrated Half-Bridge Circuit with Monolithic III-N and Group IV FET Stacking
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Solution Overview
Problem
Conventional half-bridge circuit designs for high power and high performance applications require four discrete semiconductor dies, increasing space and manufacturing costs due to the need for two III-N and two group IV FETs to implement two composite power switches.
Innovation Solution
An integrated half-bridge circuit with low side and high side composite switches is achieved through die stacking and monolithic integration of III-N and group IV FETs, where III-N FETs are cascaded with group IV FETs to form composite switches, reducing the number of required dies and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If four discrete semiconductor dies are used to implement two composite power switches, then the circuit can be assembled using conventional discrete components, but the space required and manufacturing costs increase
Solution Approach 1:
The patent merges multiple discrete FETs into integrated composite switches where III-N FETs and group IV FETs are combined on the same semiconductor die. This integration reduces the number of separate components from four discrete dies to fewer integrated devices, directly reducing the total circuit space while maintaining conventional assembly processes.
Solution Approach 2:
The patent transitions from planar discrete component layout to vertical stacking of FETs in cascode configuration on the same die. By utilizing the vertical dimension of the semiconductor structure, multiple FETs are stacked one above another, reducing the horizontal footprint and overall circuit area.
2Adaptability or versatility
If four discrete semiconductor dies are used to implement two composite power switches, then each FET can be optimized independently, but manufacturing costs increase
Solution Approach 1:
The patent combines multiple FETs into integrated composite switches on a single die, reducing the total component count from four discrete dies to fewer integrated devices. This merging reduces manufacturing complexity and costs while maintaining the ability to optimize each FET type for its specific function through careful device design and layout.
Solution Approach 2:
The integrated composite switch structure provides multi-functionality by combining high-voltage III-N FETs and low-voltage group IV FETs in a single device that can operate in both high-side and low-side configurations. This universal design reduces the need for multiple specialized discrete components.
3Adaptability or versatility
If discrete FETs are used in conventional configuration, then component selection is flexible, but parasitic inductance and resistance increase
Solution Approach 1:
The patent utilizes vertical stacking of FETs in cascode configuration, placing III-N FETs above group IV FETs on the same die. This vertical arrangement significantly reduces the current path length and loop area compared to discrete side-by-side mounting, thereby minimizing parasitic inductance and resistance while maintaining component selection flexibility.
Solution Approach 2:
The patent segments the current path into optimized zones within the integrated structure, with each FET type positioned to minimize parasitic effects in its operating region. The segmented layout allows independent optimization of high-voltage and low-voltage paths while reducing overall parasitic parameters.
Data Source
AI summary
There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches. The first and second III-N FETs are normally ON FETs, and the low side composite switch and the high side composite switch are normally OFF switches