Integrated Semiconductor Inductor Layout for Chip-Scale Miniaturization
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Solution Overview
Problem
Conventional inductor designs face challenges in integration with downsized semiconductor chips due to their size, making it difficult to achieve efficient component integration and miniaturization in modern semiconductor package devices.
Innovation Solution
A miniaturized on-chip inductor is proposed, fabricated using techniques common to semiconductor device fabrication such as lithography, etching, and deposition, featuring a conductive coil winding around a magnetic core, which reduces size and enhances integration efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional inductor designs are used, then inductor performance is achieved, but device size becomes too large for integration with downsized semiconductor chips
Solution Approach 1:
The patent merges the inductor structure with the semiconductor chip substrate by forming the inductor coil and magnetic core directly on the chip using standard semiconductor fabrication processes. This integration eliminates the need for separate discrete inductor components, thereby reducing overall device size while maintaining functional performance through optimized on-chip geometry and material selection.
Solution Approach 2:
The patent transitions from planar 2D coil structures to three-dimensional vertical coil configurations with magnetic cores extending through multiple layers. By utilizing the vertical dimension and stacking multiple metallization layers with intervening magnetic core regions, the design achieves higher inductance density within a smaller footprint, resolving the contradiction between size reduction and performance maintenance.
2Volume of moving object
If inductor size is reduced for integration, then device miniaturization is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent employs standard semiconductor fabrication processes (lithography, etching, deposition, CMP) that are already universally used in chip manufacturing to create the inductor structure. By making the inductor fabrication process universal to existing semiconductor manufacturing workflows, the patent avoids introducing specialized or complex manufacturing steps, thereby reducing manufacturing complexity despite the three-dimensional integrated structure.
Solution Approach 2:
The patent forms the inductor coil and magnetic core structures during the early stages of semiconductor fabrication, before final chip assembly. By performing preliminary actions of creating the inductor geometry and magnetic regions while the substrate is still accessible and structured, the patent simplifies subsequent processing steps and avoids complex post-fabrication assembly operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The miniaturized on-chip inductor achieves better performance and integration efficiency with reduced device size, offering improved permeability and charging performance compared to conventional inductor configurations.
Implementation Method 1
a conductive coil winding around a magnetic core
Data Source
AI summary
A semiconductor device includes: a magnetic core; a conductive coil winding around the magnetic core and electrically insulated from the magnetic core, wherein the conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines; and a connecting metal line on an outside of and electrically isolated from the conductive coil. The vertically-extending conductive vias include first conductive vias overlying a first one of the horizontally-extending conductive lines, second conductive vias overlapping the first conductive vias and underlying a second one of the horizontally-extending conductive lines, and a third conductive via between the first conductive vias and the second conductive vias. The connecting metal line is between the first conductive vias and the second conductive vias from a cross-sectional view.