Integrated JFET Structure for Low On-Resistance High-Voltage Power Devices
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Solution Overview
Problem
High-power semiconductor devices require transistors with high voltage tolerance, low on-resistance, and high power handling capacity, which existing technologies struggle to achieve effectively, especially in high voltage applications.
Innovation Solution
A semiconductor device design incorporating a semiconductor layer, epitaxial layer, source regions, sidewall body regions, gate regions, and link regions of specific conductivity types, along with a manufacturing method that includes forming these regions and using gate insulation and conductive materials to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor designs are used, then manufacturing simplicity is maintained, but voltage tolerance and power handling capacity are insufficient
Solution Approach 1:
The transistor is divided into two distinct types: a first transistor with a gate structure and a second transistor with a junction structure. This segmentation allows each transistor type to be optimized for specific functions, with the first transistor handling high-voltage switching and the second transistor providing complementary power handling, thereby achieving high voltage tolerance and power handling capacity through structural differentiation
Solution Approach 2:
The patent introduces a vertical stacked architecture where the first and second transistors are arranged in different spatial dimensions and layers. The first transistor is formed in a first region with its gate structure, while the second transistor is formed in a second region with its junction structure, utilizing three-dimensional space to achieve complex functionality while maintaining planar integration benefits
2Reliability
If high voltage tolerance is achieved through conventional means, then voltage handling improves, but on-resistance increases
Solution Approach 1:
Different regions of the semiconductor device are assigned different doping concentrations and material properties optimized for their specific functions. The first transistor region has doping and structure optimized for low on-resistance during conduction, while the second transistor region and surrounding structures are optimized for voltage blocking. This local optimization allows simultaneous achievement of low on-resistance and high voltage tolerance
Solution Approach 2:
The device employs composite semiconductor structures with different material compositions and doping profiles in different regions. The first transistor uses a gate structure with specific semiconductor materials optimized for channel control, while the second transistor uses junction structures with different material compositions optimized for voltage blocking, creating a composite device that achieves both low on-resistance and high voltage tolerance
3Power
If power handling capacity is increased, then energy processing improves, but device breakdown voltage decreases
Solution Approach 1:
The patent incorporates protective structures and design features that preemptively protect against breakdown before it occurs. The second transistor with its junction structure is positioned and designed to provide voltage blocking protection for the first transistor, and the overall device includes field plates and termination structures that distribute and reduce electric field stress, cushioning against breakdown conditions before they can cause failure
Solution Approach 2:
The second transistor acts as an intermediary protective element between the high-power first transistor and the external environment. This junction-type transistor serves as a buffer that handles voltage stress and protects the gate-structured first transistor from breakdown, enabling the device to achieve high power handling capacity while maintaining high breakdown voltage through the mediating protection of the second transistor
Data Source
AI summary
A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.