Integrated JFET Structure for Stable Pinch-Off in Smart Power ICs
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Solution Overview
Problem
Conventional high-voltage integrated JFETs suffer from unstable pinch-off voltage, which affects the stability of the breakdown voltage and increases the chip area, making them unsuitable for large-scale smart power integrated circuit manufacturing.
Innovation Solution
A method for manufacturing a device comprising a power vertical double diffused metal-oxide-semiconductor field-effect transistor (VDMOS) integrated with a junction field effect transistor (JFET), where the device includes a drain with a first conduction type region on its surface, and a second conduction type buried layer is formed in the JFET region. This structure includes forming a polysilicon layer, implanting ions to create wells, and forming metal electrodes to stabilize the pinch-off voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional integrated structure VDMOS and JFET uses substrate isolation only, then manufacturing process is simple, but breakdown point transfers and breakdown voltage stability deteriorates
Solution Approach 1:
The patent segments the substrate into multiple isolation regions by introducing P-type isolation layers between the JFET and VDMOS regions. This segmentation creates distinct electrical zones that prevent breakdown point transfer while maintaining manufacturing feasibility through standard ion implantation processes.
Solution Approach 2:
The patent applies local quality by creating P-type isolation layers specifically in the regions between JFET and VDMOS, while maintaining different doping concentrations and depths in different areas. The P-type isolation layer has specific concentration (1E14 to 1E16 atoms/cm³) and depth (1 to 5 microns) tailored to the local isolation requirements.
2Ease of manufacture
If P-type substrate with shallow longitudinal junction is used, then VDMOS structure is achieved, but JFET longitudinal channel length cannot be adjusted and pinch-off voltage becomes unstable
Solution Approach 1:
The patent transitions from controlling channel length in one dimension (horizontal) to controlling it in another dimension (vertical depth). By forming P-type isolation layers at specific depths (1 to 5 microns) below the surface, the effective longitudinal channel length of the JFET is controlled through the vertical positioning of the isolation layer rather than horizontal geometry.
Solution Approach 2:
The patent changes the doping concentration parameter of the P-type isolation layer (1E14 to 1E16 atoms/cm³) and its depth parameter (1 to 5 microns) to independently control the JFET pinch-off voltage. This allows adjustment of the pinch-off voltage from 11V to 20V by varying these parameters without changing the horizontal channel dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method significantly improves the stability of the pinch-off voltage and maintains a stable breakdown voltage, reducing the chip area and enhancing the device's performance in smart power integrated circuits.
Implementation Method 1
a P-type isolation layer is formed between the JFET and the VDMOS to isolate the depletion layer of the JFET from the cell region of the VDMOS
Implementation Method 2
The P-type isolation layer is formed by implanting ions
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain (201) with a first conduction type, while a part of the drain (201) is located in the JFET region and the other part of the drain (201) is located in the power device region; and a first conduction type region disposed on a front surface of the drain (201), while a part of the first conduction type region is located in the JFET region, and the other part of the first conduction type region is located in the power device region; the JFET region includes: a first well (205) with a second conduction type and formed in the first conduction type region; a second well (207) with a second conduction type and formed in the first conduction type region, while an ion concentration of the second well (207) is higher than an ion concentration of the first well (205) and the first conduction type is opposite to the second conduction type; a JFET source (212) with the first conduction type; a metal electrode formed on the JFET source (212), which is in contact with the JFET source (212); and a second conduction type buried layer (203) formed under the JFET source (212) and the second well (207).