Integrated Level Shifter for Wide-Range High-Speed Voltage Translation

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Solution Overview

Problem

Existing level shifters for high voltages are costly, power-intensive, and limited by speed constraints due to external implementation with significant space and component count, making high-speed operation at higher frequencies difficult and expensive.

Innovation Solution

A fully integrated level shifter that allows input voltage to float between switching stage positive and negative supply voltages, utilizing a buffer and switching stages with PMOS and NMOS FETs, and non-overlap modules to generate high and low level output signals within a wide voltage range, reducing complexity and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If level shifters are implemented external to the integrated circuit using resistors and other components, then voltage level translation between different logic levels is achieved, but the device occupies significant space, requires high component count, and increases manufacturing cost

Engineering Contradiction:

Improvevoltage level translation capabilityVSAvoidcomponent count

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the level shifter circuit with the integrated circuit itself, integrating the voltage translation functionality directly into the chip rather than using external discrete components. This consolidation eliminates the need for separate resistors and other external parts, reducing both component count and device complexity while maintaining the voltage level translation capability between different logic levels

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If level shifters are implemented external to the integrated circuit, then voltage level translation is achieved, but power consumption increases significantly

Engineering Contradiction:

Improvevoltage level translation capabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The level shifter is merged with the integrated circuit, allowing shared power management and more efficient operation. The integrated implementation enables the circuit to utilize the chip's existing power distribution network and control logic, reducing overall power consumption compared to external discrete implementations that require separate power supplies and control circuits

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If level shifters are configured with external components outside the chip, then voltage level translation is achieved, but operation at higher speeds such as 50 MHz is difficult or not possible

Engineering Contradiction:

Improvevoltage level translation capabilityVSAvoidoperating frequency

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The level shifter circuit is merged with the integrated circuit, creating a unified design where the voltage translation function is tightly coupled with the chip's internal timing and control mechanisms. This integration eliminates signal path delays associated with external connections and allows the circuit to operate at higher speeds including 50 MHz and above, as the entire signal path remains within the chip's controlled environment

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables higher speed operation, reduced space and power requirements, and lower manufacturing costs while accommodating a wide range of input voltages, allowing for efficient level shifting across different logic levels.

Implementation Method 1

a buffer configured to shift the input signal to vary between the positive first stage supply voltage and a negative first stage supply voltage to create a buffer output

Methodology Applied

Scientific EffectVoltage buffering:

Implementation Method 2

The first switching device comprises a PMOS FET and is configured to process the first stage output signal to generate a high level output signal

Methodology Applied

Scientific EffectField effect transistor switching:

Implementation Method 3

The second switching device comprises a NMOS FET and is configured to process the first stage output signal to generate a low level output signal

Methodology Applied

Scientific EffectField effect transistor switching:

Data Source

PatentUS12199606B2Level shifter with expanded voltage range

Publication Date: 2025.01.14 MACOM TECH SOLUTIONS HLDG INC

AI summary

A level shifter, configured to shift an input voltage swing from a first voltage range to a second voltage range, comprising a first stage and a switching stage, with circuitry configured in isolation wells. The first stage includes a first stage input receiving an input signal that swings between a first voltage value and a second voltage, a buffer configured to shift the input signal to vary between a third value and a fourth value, and a first stage output configured to present a first stage output signal. The switching stage comprises switching stage inputs, configured to receive the first stage output signal, switch drivers, and switching devices configured to, responsive to the driver output, generate a switching stage output signal that is a shifted version of the input signal. The switching stage output signal ranges between a fifth voltage value and a sixth voltage value.