Integrated LNA Layout Using Coupled Inductors for ESD and Matching
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Solution Overview
Problem
Conventional integrated low-noise amplifiers face challenges in achieving a compact layout, effective electrostatic discharge (ESD) protection, and maintaining good performance due to large inductor layout areas and parasitic components that degrade return loss and noise figure.
Innovation Solution
The proposed low-noise amplifier incorporates a matching network with a shunt inductor and series inductor overlapped in layout for strong mutual coupling, and a source degenerating inductor in close proximity to the shunt inductor, eliminating the need for an ESD protection circuit and reducing parasitic capacitance, while maintaining effective impedance and noise matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional inductors are used in integrated LNA, then impedance matching and noise matching can be achieved, but the layout area becomes large and cost increases
Solution Approach 1:
The patent combines multiple inductor functions into a single integrated inductor structure. The first inductor provides both impedance matching and noise matching functions simultaneously, eliminating the need for separate inductors and reducing overall layout area while maintaining manufacturing precision for impedance matching
Solution Approach 2:
The single inductor is designed to perform multiple functions: impedance matching, noise matching, and providing ESD protection path. This multi-functional design reduces the total number of components and layout area while maintaining the required manufacturing precision for impedance matching
2Reliability
If ESD protection circuit is added to protect the first NMOS transistor, then reliability improves, but return loss and noise figure are degraded
Solution Approach 1:
The patent extracts the ESD protection function from a separate ESD protection circuit and integrates it into the inductor structure itself. The inductor provides a high-impedance path that naturally redirects ESD current away from the NMOS transistor, eliminating the need for additional ESD protection components that would degrade return loss
Solution Approach 2:
The inductor acts as an intermediary element that simultaneously performs impedance matching and ESD protection. By positioning the inductor between the input node and the NMOS transistor gate, it mediates both the signal path for impedance matching and the ESD current path for protection, preventing degradation of return loss
3Ease of manufacture
If bonding pad is used for packaging the integrated circuit, then packaging is enabled, but parasitic capacitance increases and degrades performance
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance from the bonding pad into a beneficial element. By designing the inductor to work in conjunction with the bonding pad's parasitic capacitance, the overall noise matching is improved. The inductor value is selected to compensate for the parasitic capacitance, transforming what was previously a performance-degrading element into a component that enhances noise figure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a compact layout, improved ESD protection, and enhanced performance by compensating parasitic capacitance and providing an effective discharge path, resulting in better impedance and noise matching without degrading return loss or noise figure.
Implementation Method 1
a shunt inductor and a series inductor that are overlapped in layout to have a strong mutual coupling
Implementation Method 2
a source degenerating inductor that is laid out in a close proximity to the shunt inductor to have a strong mutual coupling
Data Source
AI summary
A LNA (low-noise amplifier) includes a matching network configured to provide a three-way coupling between an input node, a matched node, and a source node; a gate capacitor configured to provide AC (alternate current) coupling between the matched node and a gate node; a cascode amplifier configured to receive a gate voltage at the gate node and output an output voltage at an output node in accordance with a source degeneration at the source node; and a load network connected to the output node, wherein the matching network having a shunt inductor and a series inductor that are overlapped in layout to have a strong mutual coupling and a source degenerating inductor that is laid out in a close proximity to the shunt inductor to have a strong mutual coupling.