Integrated Mask Synthesis for Lithography and Fabrication Effects
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Solution Overview
Problem
Existing semiconductor wafer manufacturing processes face challenges due to separate corrections for mask fabrication and wafer lithography effects, leading to inefficiencies and increased computational overhead.
Innovation Solution
An integrated model that simulates both mask fabrication and wafer lithography processes together, eliminating the need to predict the patterned layout of the lithographic mask, thereby reducing data handling and computational requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate corrections for mask fabrication and wafer lithography effects are applied, then manufacturing precision is improved, but device complexity and computational overhead increase
Solution Approach 1:
The patent combines separate mask fabrication correction and wafer lithography correction processes into a single integrated model. This unified approach simultaneously accounts for both mask fabrication effects and wafer lithography effects, reducing the number of separate correction steps while maintaining or improving pattern accuracy on the wafer.
Solution Approach 2:
The integrated model serves multiple functions: it corrects for mask fabrication effects, wafer lithography effects, and their interactions all within a single computational framework. This multi-functional approach eliminates the need for separate correction processes and reduces overall computational overhead.
2Manufacturing precision
If separate corrections for mask fabrication and wafer lithography effects are applied, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent merges multiple correction processes into one integrated model that simultaneously handles mask fabrication effects and wafer lithography effects. This consolidation reduces the total computational time required while maintaining pattern accuracy, thereby improving design turnaround time and overall productivity.
3Manufacturing precision
If the mask pattern is predicted and used as input to wafer lithography model, then manufacturing precision is improved, but loss of time and computational resources increase
Solution Approach 1:
The patent extracts and eliminates the intermediate step of predicting the mask pattern. Instead of computing the mask pattern and then using it as input to the wafer lithography model, the integrated model directly computes the wafer pattern by accounting for both mask fabrication and wafer lithography effects in a single computational pass, saving significant computational time.
Solution Approach 2:
The integrated model performs preliminary accounting for mask fabrication effects within the same computational framework that handles wafer lithography effects. This preliminary integration eliminates the need for sequential processing and reduces overall computational time while maintaining pattern accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the quality of the final printed wafer patterns by better modeling interactions between mask fabrication and wafer lithography processes, decreasing CPU processing power and design turnaround time.
Implementation Method 1
Each feature image is convolved with a corresponding M3D filter. The M3D filter represents an electromagnetic scattering effect of that feature image in the wafer lithography process
Data Source
AI summary
In some aspects, an integrated model accounts for effects from both the mask fabrication process and the wafer lithography process. The aerial image incident on the wafer, the pattern printed on the wafer, and/or measures of the foregoing are estimated using an integrated three-dimensional mask (M3D) model, as follows. The shapes in the mask fabrication description are partitioned into feature images. Each feature image is convolved with a corresponding M3D filter. The M3D filter represents an electromagnetic scattering effect of that feature image in the wafer lithography process, and the feature image and/or M3D filter account for effects on the layout geometry from the mask fabrication process. This is done without estimating the mask pattern printed on the lithographic mask. The mask fabrication description is modified based on differences between the estimated lithography results and corresponding target results.