Integrated Memory BIST Circuit Design for Chip Area Reduction
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Solution Overview
Problem
The miniaturization of semiconductor devices is hindered by wiring congestion and impaired wiring characteristics due to the placement of memory BIST circuits, which complicates timing adjustment and increases the chip area, especially when the BIST pattern generator is separated from the memory circuits, leading to inefficient use of space and increased TAPs.
Innovation Solution
A designing method where the memory BIST circuit is integrated within the memory circuit, with a block of a pulse generator and input/output circuits arranged adjacently, and a pattern generator connected to the pulse generator, and comparators arranged with the same pitch as input/output circuits, optimizing signal wiring and reducing unnecessary regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the memory BIST circuit is arranged in a vicinity of the memory circuit with unit cells placed between them, then timing verification is easier, but wiring congestion increases and chip area cannot be reduced
Solution Approach 1:
The patent merges the memory BIST circuit with the memory circuit by integrating the BIST circuit into the same memory block structure. The BIST circuit shares the same cell array and wiring resources as the normal memory circuit, eliminating the need for separate unit cell regions and reducing overall chip area while maintaining timing verification capabilities.
Solution Approach 2:
The memory circuit is designed to serve dual purposes: normal memory operation and BIST functionality. The same cell array, word lines, and bit lines are used for both memory access and self-test operations, eliminating redundant wiring and reducing chip area while maintaining ease of timing verification.
2Reliability
If the BIST pattern generator is arranged between memory circuits with unit cell regions, then the memory BIST circuit can be complete, but wiring characteristics are impaired due to power supply wiring requirements
Solution Approach 1:
The BIST pattern generator is integrated into the same memory block as the cell array, sharing power supply wiring and signal paths. This eliminates the need for separate power supply routing that would impair wiring characteristics, while maintaining complete BIST functionality through shared memory structures.
3Area of stationary object
If the comparator of the memory BIST circuit is built in the memory circuit, then circuit area is reduced and fast operation is realized, but the BIST pattern generator must be arranged between memory circuits creating useless regions
Solution Approach 1:
The entire BIST circuit including pattern generator, cell array, and comparator is merged into a single integrated memory block structure. This eliminates separate BIST blocks that would create useless regions in wells, as all components share the same memory block footprint and wiring infrastructure.
4Ease of manufacture
If the region where unit cells can be placed is set between memory circuits for BIST circuit arrangement, then BIST circuit placement is enabled, but TAPs increase due to separate well intervals
Solution Approach 1:
The BIST circuit is integrated into the same memory block as the cell array, sharing the same well structure and TAP connections. This eliminates the need for separate unit cell regions between memory circuits, thereby reducing the number of TAPs required while maintaining ease of BIST circuit placement.
Data Source
AI summary
A memory circuit with a built-in memory BIST circuit is created by: arranging a block of a clock pulse generator and a plurality of blocks of input/output circuits each corresponding to each of inputted/outputted bits adjacently in a first direction; arranging a block of a BIST pattern generator of the memory BIST circuit which is laid out so that signal wiring is connected by being arranged adjacently and performs generation of a test pattern, adjacently to the block of the clock pulse generator in a second direction; and arranging a plurality of blocks of comparators of the memory BIST circuit which are laid out so that signal wirings are connected by being arranged adjacently and compare an output value and an expected value, adjacently to the plurality of blocks of the input/output circuits in the second direction with the same pitch as that of the input/output circuits.