Integrated Memory High Voltage Logic Transistors Same Stack Height
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Solution Overview
Problem
Integrating memory array, high voltage devices, and high speed logic circuit elements into a single integrated circuit (IC) is challenging due to differing device requirements, complicating the manufacturing process and increasing costs, while also potentially degrading the reliability of memory and high voltage devices.
Innovation Solution
A semiconductor device with distinct regions for memory, high voltage, and logic transistors, all having substantially the same stack height, allowing for reliable integration without compromising device reliability or requiring additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory array, high voltage devices and logic circuit elements are integrated into a single IC, then device functionality and embedding capability are improved, but manufacturing process complexity and cost increase
Solution Approach 1:
The patent applies local quality by creating distinct regions (first region for memory, second region for high voltage devices, third region for logic circuits) with different well structures and doping characteristics. Each region is optimized for its specific device type while maintaining overall integration, allowing each area to have the precise properties needed for its function without compromising the entire chip.
Solution Approach 2:
The patent segments the integrated circuit into separate functional regions with dedicated well structures. Memory devices use first and second wells in the first region, high voltage devices use first and second wells in the second region, and logic circuits use first and second wells in the third region. This segmentation allows independent optimization of each device type while maintaining single-chip integration.
2Adaptability or versatility
If memory array, high voltage devices and logic circuit elements are integrated into a single IC, then device functionality is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple device types (memory, high voltage, logic) into a single integrated circuit chip with unified well formation processes. By combining the fabrication of different device types in one manufacturing flow using shared process steps for creating first and second wells across all regions, the patent reduces overall manufacturing cost compared to separate fabrication processes.
Solution Approach 2:
The patent creates a universal well structure that serves multiple functions across different device types. The first and second wells are formed using the same processes throughout the chip, serving both memory devices and high voltage devices, thereby reducing the need for separate specialized manufacturing processes and lowering overall production cost.
3Adaptability or versatility
If different device types are integrated in a single chip, then embedding capability is improved, but device reliability degrades
Solution Approach 1:
The patent applies local quality by providing region-specific well structures optimized for each device type's reliability requirements. Memory devices in the first region receive dedicated well engineering, high voltage devices in the second region receive appropriate well structures for voltage handling, and logic circuits in the third region receive optimized wells for switching performance, thereby maintaining high reliability across all integrated devices.
Data Source
AI summary
A device and methods for forming a device are disclosed. The device includes a substrate having first, second and third regions. The first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region. A memory cell which includes a memory transistor having a first stack height (TSM) is disposed in the first region. A high voltage (HV) transistor having a second stack height (TSHV) is disposed in the second region and a logic transistor having a third stack height (TSL) is disposed in the third region. The first, second and third stack heights are substantially the same across the substrate.