Integrated Memory Logic Fabrication via Unified CMOS Process
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Solution Overview
Problem
The complexity in fabricating integrated composite chips that combine memory and logic circuits, due to the need to simultaneously consider fabrication aspects of both, poses a significant technical challenge.
Innovation Solution
A semiconductor device and method that integrate a memory cell and logic transistors on a single substrate, with the logic transistors controlling the memory cell's operation, allowing for simultaneous fabrication of DRAM and logic circuits using a CMOS process, reducing memory space requirements and eliminating external data exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory and logic circuits are combined in one chip to increase packing density, then device integration and speed are improved, but fabrication complexity increases due to needing to simultaneously consider both memory and logic circuit fabrication aspects
Solution Approach 1:
The patent merges memory circuit fabrication and logic circuit fabrication into a single unified CMOS fabrication process. By integrating both circuit types on the same substrate using the same manufacturing steps, the patent achieves high device packing density while avoiding the fabrication complexity that would arise from separate processing streams or system-in-package approaches.
2Device complexity
If memory and logic circuits are fabricated separately and stacked using system-in-package, then fabrication complexity is reduced, but device size increases and external data exchange is required
Solution Approach 1:
The patent combines memory and logic circuits on a single substrate, eliminating the need for system-in-package stacking. This integration reduces the overall device footprint while maintaining fabrication simplicity through unified CMOS processing, avoiding both the size penalty and external interface requirements of separate stacking approaches.
3Adaptability or versatility
If separate fabrication processes are used for memory and logic circuits, then each can be optimized independently, but manufacturing variations increase and process alignment becomes difficult
Solution Approach 1:
The patent employs a universal CMOS fabrication process that serves both memory and logic circuit fabrication simultaneously. This multi-functional approach ensures that both circuit types are manufactured under identical process conditions, eliminating alignment issues and reducing manufacturing variations while still allowing circuit-specific optimization through layout and device design choices.
Data Source
AI summary
The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.