Integrated Memory Management Device for Cache and Main Memory Access
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Solution Overview
Problem
Conventional memory management systems face challenges in optimizing memory access hierarchies, particularly in managing NAND Flash memory, due to the complexity of operations across different memory hierarchies, which makes it difficult to control bad blocks and ensure equal access to all blocks, leading to inefficiencies in data management.
Innovation Solution
An integrated memory management device within a microprocessing unit (MPU) that includes a memory management unit (MMU), cache controllers, and an access history storage, which converts logical addresses to physical addresses and manages access to both cache and main memory, optimizing memory access by simplifying data movement and controlling block access based on rewrite frequency and address relations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the MPU executes operations across multiple memory hierarchies (cache memory, main memory, NAND Flash memory), then data can be accessed from different storage levels, but the complexity of managing different memory hierarchies increases and optimization between hierarchies becomes difficult
Solution Approach 1:
The patent combines the MMU and cache controller into a single integrated memory management device. This merging eliminates the need for separate management operations for cache memory and main memory, reducing the number of memory hierarchies from multiple to a unified two-level hierarchy (integrated memory management device + NAND Flash memory). The integration allows the same hardware unit to handle both virtual-to-physical address conversion and cache control, thereby simplifying the overall system complexity while maintaining access capabilities across different memory levels.
Solution Approach 2:
The integrated memory management device performs multiple functions that were previously handled by separate components. It simultaneously executes virtual memory management (address conversion), cache control (hit/miss judgment, data transfer), and memory hierarchy coordination. This multi-functionality reduces the number of operations needed across different memory hierarchies and enables unified optimization of memory access patterns.
2Reliability
If the MPU uses separate control operations for cache memory and NAND Flash memory, then each memory type can be managed independently, but it becomes difficult to realize control of managing bad blocks and equal access distribution
Solution Approach 1:
By integrating the cache controller and MMU, the patent enables unified control of memory operations. The integrated device can now implement bad block management and equal access distribution across NAND Flash blocks while simultaneously managing cache operations. This unified control eliminates the previous separation that prevented coordinated management of defective blocks and access patterns across different memory hierarchies.
Solution Approach 2:
The integrated memory management device implements feedback mechanisms to track access patterns and block status across the entire memory system. By monitoring which NAND Flash blocks are defective and which are frequently accessed, the device can dynamically adjust address mappings and cache replacement policies to avoid bad blocks and distribute access evenly across healthy blocks, thereby improving reliability without requiring complex separate control operations.
3Adaptability or versatility
If the system maintains multiple memory hierarchies for accessing cache memory and main memory, then data access flexibility is improved, but the number of operations and access time increase
Solution Approach 1:
The integration of MMU and cache controller reduces the number of memory hierarchies from three (cache, main memory, NAND Flash) to two (integrated memory management device, NAND Flash). This reduction eliminates intermediate access steps and reduces the number of operations required for memory access, thereby decreasing access time while preserving data access flexibility through the unified device's ability to handle both virtual addressing and cache management.
4Productivity
If the MPU performs virtual memory management and Flash File System controls separately, then each memory management function can be optimized independently, but the overall optimization between different hierarchy operations becomes difficult
Solution Approach 1:
The patent merges virtual memory management and Flash File System controls into a single integrated memory management device. This integration enables coordinated optimization of operations across different memory hierarchies. The unified device can simultaneously consider virtual address translation requirements and NAND Flash-specific constraints (such as bad blocks and wear leveling) when managing memory operations, thereby improving overall productivity without requiring complex separate management structures.
Data Source
AI summary
An example of a device comprises a first MMU converting a logical address into a physical address for a cache, a controller accessing the cache based on the physical address for the cache, a first storage storing history data showing an access state to a main memory outside a processor, a second storage storing relation data showing a relationship between a logical address and a physical address in the main memory, and a second MMU converting a logical address into a physical address for the main memory based on the history and relation data and accessing the main memory based on the physical address for the main memory. The first and second MMU, controller, first storage, second storage are included in the processor.