Integrated Memory Management Device for NAND Flash Access Optimization
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Solution Overview
Problem
Conventional information processing devices face challenges in optimizing memory access operations across multiple layers of the memory hierarchy, particularly when managing NAND type flash memory, leading to inefficient data access and increased processing time due to the complexity of managing bad blocks and cache memory changes.
Innovation Solution
A memory management device that integrates a memory management unit (MMU), cache controller, and main memory MMU to optimize memory access by using a composite main memory with a nonvolatile semiconductor memory, reducing the number of memory hierarchies and minimizing access to secondary memory devices by converting logical addresses to physical addresses and storing address conversion data for efficient data placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional memory hierarchy with multiple layers (cache memory, main memory, secondary memory) is used, then storage capacity is increased, but memory access complexity and processing time increase
Solution Approach 1:
The patent merges the cache memory controller and main memory controller into a single integrated memory management device that manages both cache memory and NAND type flash memory. This integration simplifies the memory access control structure by eliminating the need for separate controllers in different layers, thereby reducing device complexity while maintaining the multi-layer memory hierarchy for increased storage capacity.
Solution Approach 2:
The integrated memory management device performs multiple functions including cache memory management, main memory management, and address conversion for both cache memory and NAND type flash memory. This multi-functional approach allows a single device to handle diverse memory access operations that would traditionally require separate specialized controllers, thus reducing overall system complexity.
2Reliability
If separate control functions for bad block management and cache memory data changeover are implemented in different layers, then reliability is improved, but coordination difficulty increases
Solution Approach 1:
The patent combines bad block management control and cache memory data changeover control into a single integrated memory management device. This integration enables coordinated management of both functions within the same control unit, eliminating the coordination difficulties that would arise from implementing these controls in separate layers while maintaining the reliability benefits of dedicated control for each function.
3Quantity of substance
If the number of memory hierarchy layers is increased to access secondary memory devices, then storage capacity is improved, but processing time increases
Solution Approach 1:
The integrated memory management device reduces processing time by consolidating control operations for cache memory and NAND type flash memory access into a single device. This integration enables more efficient coordination between memory layers, reducing the time overhead associated with managing multiple separate control functions while maintaining the multi-layer hierarchy for enhanced storage capacity.
Data Source
AI summary
A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.