Integrated Memory Cell Array Layout for Lower-Power OTP Storage
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Solution Overview
Problem
Nonvolatile memory devices face challenges in achieving low power consumption and reduced area due to the separate implementation of memory cell arrays and one-time program (OTP) cell arrays, which increase power consumption and area.
Innovation Solution
The memory device integrates main memory cells, OTP cells, and reference resistors with specific electrical connections and voltage applications to optimize operations, reducing power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cell array and OTP cell array are implemented separately, then read and write operations can be performed independently, but power consumption increases and area increases
Solution Approach 1:
The patent merges the memory cell array and OTP cell array into a single integrated array structure. Main memory cells and OTP cells share common word lines, bit lines, and source lines, allowing both read and write operations to be performed within the same physical structure. This integration eliminates the need for separate arrays, thereby reducing overall area and power consumption while maintaining operational independence through control signal management.
2Adaptability or versatility
If memory cell array and OTP cell array are implemented separately, then specific operations can be optimized independently, but area increases
Solution Approach 1:
The patent combines both cell types into a unified array architecture where main memory cells and OTP cells coexist and share common addressing and data transmission lines. This merging strategy reduces the total area required for the memory device while preserving the ability to optimize specific operations through control logic that directs read or write operations to the appropriate cell type.
Solution Approach 2:
The integrated array structure enables word lines, bit lines, and source lines to serve multiple functions simultaneously - they can be used for reading from main memory cells, writing to OTP cells, or performing other operations depending on the control signals applied. This multi-functionality eliminates the need for dedicated separate arrays, reducing area while maintaining operational flexibility.
3Ease of operation
If separate arrays are used, then read operations for main memory cells and write operations for OTP cells can be performed independently, but power consumption increases
Solution Approach 1:
The patent employs dynamic control signals to manage the operation modes of the integrated array. Control logic selectively activates different cell types and adjusts word line and bit line voltages based on whether a read or write operation is required. This dynamic management allows the system to perform independent read and write operations while optimizing power consumption by activating only the necessary circuits for each operation.
Data Source
AI summary
Disclosed is a memory device which includes a plurality of memory cells, word lines electrically connected to rows of the plurality of memory cells, and bit lines and source lines electrically connected with columns of the plurality of memory cells. The plurality of memory cells include main memory cells of a main cell area that are configured to support a read operation and a write operation, and one time program cells of a one time program (OTP) cell area that are configured to support the write operation once and a one time program reference cell for the read operation of the one time program cells. Each of the main memory cells is electrically connected to a respective word line, and each of the one time program cells is electrically connected to at least two respective word lines of the word lines.