Integrated MEMS Device Bonding for Structural Reliability
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Solution Overview
Problem
The manufacturing process of optical array-type MEMS devices is hindered by the need for low-temperature materials and processes to avoid affecting circuitry, leading to reduced structural reliability, surface roughness, and performance due to the limitations imposed by the recess in the reflective mirror and the flexible structure's design.
Innovation Solution
An integrated MEMS device is created by bonding a circuit chip with a device chip using patterned bonding layers and sacrificial layers, allowing for hermetic vacuum spaces and enabling the use of more robust materials and processes, with the first structural layer being hidden under the second structural layer to improve light usage and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-temperature materials and processes are used to manufacture optical array-type MEMS devices, then the circuitry on the circuit wafer is protected from damage, but the structural reliability, surface roughness, and surface topography of the device are degraded
Solution Approach 1:
The device is divided into two separate wafers: a first wafer containing the optical array-type MEMS device and a second wafer containing the circuitry. These wafers are processed independently and then bonded together, allowing each wafer to be manufactured using optimal processes for its specific requirements without compromising the other.
Solution Approach 2:
A bonding layer is introduced as an intermediary between the first wafer and the second wafer. This bonding layer enables the connection of the two wafers after they have been separately processed, allowing the use of high-temperature materials and processes on the first wafer without affecting the circuitry on the second wafer.
2Manufacturing precision
If micromachining processes are performed on the circuit wafer to form the reflective mirror, then the optical array-type device is manufactured, but recesses are formed in the reflective mirror which prevent effective light reflection
Solution Approach 1:
The manufacturing process is segmented so that the reflective mirror is formed on a separate first wafer that is dedicated to the optical array-type MEMS device. This allows the reflective mirror surface to be fully planarized without the need for recessed anchor structures, maximizing light reflection efficiency while the circuit wafer is processed separately.
Solution Approach 2:
The problem is solved by transitioning from a single-wafer three-dimensional integration approach to a multi-wafer stacking approach. The anchor structures are formed in a different spatial arrangement on the first wafer, allowing the reflective mirror surface to remain planar and fully functional for light reflection.
3Reliability
If the flexible structure is hidden under the reflective mirror to improve device performance, then the light reflection area is maximized, but the manufacturing process becomes more challenging
Solution Approach 1:
The flexible structure and reflective mirror are fabricated on the first wafer as integrated components, with the flexible structure positioned underneath the reflective mirror surface. This segmentation allows the reflective mirror to maintain its full planar surface for optimal light reflection while the flexible structure provides the necessary mechanical support and actuation functionality.
Solution Approach 2:
The flexible structure is nested underneath the reflective mirror, with the reflective mirror positioned on top of the flexible structure. This nested arrangement allows both components to coexist in a space-efficient manner, maximizing the light reflection area while maintaining the device's mechanical functionality.
Data Source
AI summary
An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.