Integrated MIM Capacitor Structure With Shared Ground Vias
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Solution Overview
Problem
Existing MIM capacitor structures in semiconductor ICs have separate logic and I/O MIM capacitors with distinct ground contact vias, which reduces circuit design flexibility and increases the MIM structure footprint.
Innovation Solution
An integrated MIM structure is proposed, featuring a low voltage region coupled to logic transistors and a high voltage region coupled to I/O transistors, with both regions overlapping at a third region. This structure includes at least three conductor plate layers interleaved by insulator layers, with vias electrically coupled to different subsets of conductor plate layers, allowing shared ground vias between logic and I/O MIM regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate logic and I/O MIM capacitors with distinct ground contact vias are used, then each capacitor can be independently designed, but the MIM structure footprint increases and circuit design flexibility decreases
Solution Approach 1:
The patent combines logic MIM capacitor and I/O MIM capacitor into a single integrated MIM structure, allowing both capacitors to share common ground contact vias. This merging reduces the total footprint area while maintaining the ability to independently design and operate each capacitor at different voltages, thereby resolving the contradiction between footprint size and design flexibility.
Solution Approach 2:
The integrated MIM structure implements multi-functionality by enabling a single structure to serve both logic and I/O capacitor functions. The structure accommodates different operating voltages and electrical characteristics for each capacitor type while sharing common ground vias, thus improving adaptability without proportionally increasing footprint area.
2Device complexity
If separate ground contact vias are used for logic and I/O MIM capacitors, then electrical isolation is maintained, but the overall structure complexity and footprint increase
Solution Approach 1:
The patent merges the ground contact via structures for logic and I/O MIM capacitors into shared common ground vias. This consolidation reduces the total number of vias required and simplifies the overall structure, thereby reducing device complexity and footprint area simultaneously.
Solution Approach 2:
The patent employs vertical stacking of conductor plate layers in the third dimension to achieve electrical isolation between logic and I/O capacitors without requiring separate ground vias in the planar dimension. This dimensional transition allows sharing of ground contact structures while maintaining electrical separation, reducing both complexity and footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated MIM structure achieves a smaller footprint and increased circuit design flexibility by allowing shared ground vias between logic and I/O MIM regions, while accommodating different operating voltages through varying insulation layer materials and thicknesses.
Implementation Method 1
A device structure includes a metal-insulator-metal (MIM) stack including a plurality of conductor plate layers interleaved by a plurality of insulator layers
Implementation Method 2
a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers
Implementation Method 3
the first region and the second region overlapping at a third region... At least one of the third subset of the plurality of conductor plate layers vertically overlaps with at least one of the first subset of the plurality of the conductor plate layers and at least one of the second subset of the plurality of the conductor plate layers
Data Source
AI summary
A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack that includes a plurality of conductor plate layers interleaved by a plurality of insulator layers. The MIM stack includes a first region and a second region and the first region and the second region overlaps in a third region. The MIM stack further includes a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers, and a ground via passing through the third region and electrically coupled to a third subset of the plurality of conductor plate layers.