Integrated MOS Cell Disabling for Heat and On-State Resistance
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Solution Overview
Problem
MOS transistors with cellular structures face limitations in their Safe Operating Area (SOA) due to increased drain/source on-state resistance when dummy regions are used to dissipate heat, which adversely affects their performance, especially when operating in the linear region.
Innovation Solution
The integration of disabling structures within selected cells that can be switched between non-conductive and conductive states based on the operating conditions of the MOS transistor, allowing for dynamic control of cell activity to manage heat dissipation and resistance, thereby optimizing the SOA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If source regions are removed in some cells to act as dummy regions for heat dissipation, then thermal limitation is improved, but drain/source on-state resistance increases
Solution Approach 1:
The patent introduces a dynamic control mechanism where the gate element can selectively activate or deactivate individual cells based on operating conditions. This allows the MOS transistor to adapt its structure dynamically: during high-voltage operations, certain cells are disabled to reduce heating, while during linear operations, all cells remain active to maintain low on-state resistance. The disabling structure includes a gate element with coupled and uncoupled portions that can be controlled independently.
Solution Approach 2:
The patent applies local quality by creating different operational states for different cells within the same MOS transistor structure. Specifically, selected cells are equipped with disabling structures that allow them to be selectively deactivated, while other cells remain fully operational. This enables localized heat management where only specific cells are disabled when needed, rather than uniformly affecting all cells.
2Temperature
If cells are selectively disabled to reduce heating during high-voltage operations, then thermal limitation is improved, but device complexity increases
Solution Approach 1:
The patent segments the gate element into coupled and uncoupled portions, and divides the MOS transistor into multiple cells with selective disabling capability. Each cell can be independently controlled through the disabling structure, allowing precise thermal management. The segmentation enables the system to manage heat by controlling individual cells rather than the entire device, reducing the need for complex external control mechanisms.
Solution Approach 2:
The disabling structure is integrated within the MOS transistor itself, using the gate element's own structure to control cell activation. The coupled gate portion receives control signals that automatically disable specific cells when voltage thresholds are exceeded, enabling the device to self-regulate its thermal state without requiring external control circuits.
Data Source
AI summary
An integrated device includes at least one MOS transistor having a plurality of cells. In each of one or more of the cells a disabling structure is provided. The disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or to be in a conductive condition otherwise. A system comprising at least one integrated device as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device is proposed.