Integrated MRAM Cache Module for Low Power Memory Subsystems
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Solution Overview
Problem
Conventional memory subsystem designs face challenges with SRAM's high leakage and area consumption for on-chip caches and DRAM's volatility and limited scalability for off-chip main memory, leading to increased power consumption and bandwidth stress.
Innovation Solution
Integrated MRAM modules are used, comprising MRAM last-level cache and MRAM main memory, which offer high speed, low power, and scalability, replacing SRAM and DRAM technologies to simplify interfaces and reduce area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM is used for on-chip last-level cache, then speed and performance are improved, but area consumption and leakage increase
Solution Approach 1:
The patent merges the last-level cache and main memory into a single unified memory structure, both implemented using MRAM technology. This eliminates the need for separate SRAM cache and DRAM memory blocks, reducing total area while maintaining high-speed access characteristics throughout the memory hierarchy.
Solution Approach 2:
The patent changes the fundamental technology parameter from SRAM/DRAM to MRAM, which offers superior characteristics including non-volatility, lower leakage, and comparable speed to SRAM. This parameter change enables achieving high cache speed without the area and leakage penalties of traditional SRAM.
2Quantity of substance
If DRAM is used for off-chip main memory, then density and cost are improved, but volatility and refresh power consumption increase
Solution Approach 1:
The patent changes the memory technology parameter from volatile DRAM to non-volatile MRAM for main memory implementation. This eliminates the need for continuous refresh operations, removing the associated power consumption while maintaining high density characteristics inherent to MRAM technology.
3Productivity
If SRAM and DRAM are used in conventional memory subsystem, then performance and density are improved, but power consumption and bandwidth stress increase
Solution Approach 1:
The patent creates a universal memory architecture where MRAM serves multiple functions simultaneously - acting as both last-level cache and main memory. This eliminates the need for separate optimized structures for different memory functions, reducing overall system complexity and power consumption while maintaining high performance across all memory operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MRAM modules provide improved performance and energy efficiency by reducing power consumption and increasing flexibility in memory architecture, while supporting higher bandwidth demands without the need for extensive redesign.
Implementation Method 1
magnetoresistive random access memory (MRAM) module comprising a MRAM last level cache and a MRAM main memory
Data Source
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AI summary
Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved scalability.