Integrated Multi-Bit Flip-Flop with Mixed Driving for Low-Voltage Timing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

As ICs become smaller and more complex, the decreasing operating voltages affect IC performance, particularly in level shifter circuits operating in different voltage domains, leading to issues with power consumption and timing violations.

Innovation Solution

A mixed driving multi-bit flip-flop (MBFF) configuration is implemented, where flip-flops within the MBFF have different driving current capabilities based on varying numbers of fins and threshold voltages, reducing duplicate inverters and optimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If operating voltage is decreased to enable smaller and more complex ICs, then integration density is improved, but timing violations occur in level shifter circuits

Engineering Contradiction:

Improveintegration densityVSAvoidtiming violations

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by providing different driving current capabilities to different flip-flops within the same multi-bit flip-flop structure. Specifically, some flip-flops are configured with higher driving current capability (using more fins) than others, allowing each flip-flop to be optimized for its specific timing requirements while operating at the same reduced voltage, thereby resolving timing violations without sacrificing integration density

Inventive Principle:

Principle #3Local quality

2Area of moving object

If operating voltage is decreased to enable smaller and more complex ICs, then integration density is improved, but power consumption increases

Engineering Contradiction:

Improveintegration densityVSAvoidpower consumption

Core Design Contradiction:

Area of moving objectVSUse of energy by moving object

Solution Approach 1:

The patent applies parameter changes by varying the number of fins in different flip-flops to create different driving current capabilities. This allows the circuit to operate at lower voltages with reduced power consumption while maintaining timing integrity. The parameter change in fin count enables each flip-flop to contribute differently to overall power consumption based on its specific function and timing requirements

Inventive Principle:

Principle #35Parameter changes

3Area of stationary object

If duplicate inverters are removed to reduce area occupancy, then area efficiency is improved, but timing control capability is reduced

Engineering Contradiction:

Improvearea occupancyVSAvoidtiming control capability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent applies segmentation by dividing the multi-bit flip-flop into independent flip-flop units, each with its own driving current capability determined by fin count. This segmentation allows timing control to be distributed across individual flip-flops rather than relying on centralized inverter stages, enabling area reduction while maintaining timing control capability through localized optimization

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12400067B2Integrated circuit and method of forming same and a system

Publication Date: 2025.08.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A multi-bit flip-flop includes a first flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The first flip-flop includes a first set pin configured to receive a first set signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together. The first flip-flop and the second flip-flop are configured to share at least a first clock pin.