Integrated Multiply Divide Circuit for Signed Unsigned Values
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Solution Overview
Problem
Existing multiply and divide circuits are often limited to performing either multiplication or division operations and struggle to handle both signed and unsigned binary values simultaneously, leading to inefficiencies and the need for multiple circuits, which is costly and inefficient in terms of hardware space.
Innovation Solution
A multiply and divide circuit is designed to interactively perform both multiplication and division operations on any combination of signed and unsigned binary values using an instruction register, input registers, an Arithmetic Logic Unit (ALU), and configuration circuitry, with a state machine controlling the operation to handle different states for multiplication and division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate multiply and divide circuits are implemented to handle both operations, then operational capability is improved, but hardware space and cost increase
Solution Approach 1:
The patent implements a single circuit that can perform both multiplication and division operations by using configuration circuitry to reconfigure the ALU's operation mode based on control signals. The same ALU, input registers, and control logic are used for both multiply and divide operations, eliminating the need for separate dedicated circuits and reducing hardware space while maintaining full operational capability for both functions
Solution Approach 2:
The circuit employs dynamic reconfiguration through configuration circuitry that changes the ALU's behavior based on the operation type. Control signals dynamically switch the ALU between multiplication and division modes, and the configuration circuitry adjusts data flow paths and register configurations accordingly, allowing one circuit to adaptively perform multiple functions without requiring static dedicated hardware for each operation
2Measurement precision
If multiple circuits are used to handle signed and unsigned values, then processing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent uses a single ALU and control logic structure that can process both signed and unsigned binary values by interpreting control signals that indicate the operand types. The configuration circuitry adjusts the ALU's interpretation of input data and output results based on whether signed or unsigned arithmetic is required, eliminating the need for separate circuits while maintaining processing accuracy for both formats
Solution Approach 2:
The circuit changes operational parameters through control signals that indicate whether signed or unsigned arithmetic should be performed. The configuration circuitry modifies data interpretation parameters, such as sign bit handling and two's complement conversion, allowing the same hardware to accurately process different data types by dynamically adjusting its operational mode rather than requiring separate dedicated circuits
3Area of stationary object
If a single circuit performs both multiply and divide operations, then hardware space is reduced, but operational flexibility may be compromised
Solution Approach 1:
The patent employs dynamic reconfiguration through configuration circuitry that responds to control signals to switch the ALU between multiplication and division modes. The same hardware resources are dynamically allocated to different operations based on real-time requirements, maintaining full operational flexibility for both multiply and divide functions while using minimal hardware space through time-multiplexed resource sharing
Data Source
AI summary
The principles of the present invention relate to a multiply and divide circuit configured to interactively multiply and/or divide. The circuit may handle signed and unsigned values. The circuit comprises an instruction register configured to store a multiply or divide instruction, at one input register configured to store the multiply or divide operands, an Arithmetic Logic Unit (“ALU”) configured to add provided values, and configuration circuitry. The configuration circuitry responds to the instructions and performs the multiply or divide operation by iteratively providing values to the ALU.