Integrated Multiplexer Flip-Flop for Reduced Logic Depth
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Solution Overview
Problem
Existing digital circuits face challenges in reducing logic depth and increasing frequency, particularly in high-performance applications like multi-gigahertz processors, where current multiplexer flip-flop circuitry is inefficient, leading to higher costs and limited frequency speedup.
Innovation Solution
The approach involves integrating the first stage of the multiplexer into the flip-flop and moving the second stage from data logic to clock logic, utilizing a master-slave latch structure with NOR gates and combinatorial logic blocks to reduce logic depth and enhance clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multiplexer flip-flop circuitry is used, then circuit functionality is maintained, but logic depth increases and frequency decreases
Solution Approach 1:
The patent combines the multiplexer and flip-flop into a single integrated circuit unit, merging previously separate components to reduce overall logic depth and improve timing performance
Solution Approach 2:
The patent moves the second stage of the multiplexer from the data logic path to the clock logic path, effectively changing the dimensional organization of logic stages to remove critical path delays
2Productivity
If logic depth is reduced by integrating multiplexer into flip-flop, then clock frequency increases, but circuit complexity increases
Solution Approach 1:
The integrated multiplexer flip-flop circuit performs multiple functions (multiplexing and flip-flop operation) within a single unified structure, reducing the need for separate components and interconnections
Data Source
AI summary
In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.