Integrated Nanosheet Contacts for Wider Semiconductor Process Margins
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Solution Overview
Problem
Existing semiconductor devices face challenges in securing process margins for forming gate contacts, source/drain contacts, and bottom vias, and simplifying the processes involved.
Innovation Solution
A semiconductor device design featuring a first lower interlayer insulating layer with an insulating pattern and nanosheets, surrounded by gate electrodes, where source/drain and gate contacts are integrally formed, and a bottom via is connected to both, simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contact, source/drain contact, and bottom via are formed as separate structures, then each component can be independently optimized, but the fabrication process complexity increases and process margins are reduced
Solution Approach 1:
The patent merges the gate contact, source/drain contact, and bottom via into a single integrated contact structure. This unified structure is formed through a single fabrication process, eliminating the need for separate formation steps for each component. The integration reduces process complexity and variability, thereby improving process margins and manufacturing reliability.
Solution Approach 2:
The integrated contact structure serves multiple functions simultaneously: it provides electrical connection for the gate, source/drain regions, and bottom via. This multi-functional design eliminates the need for separate specialized contacts, simplifying the fabrication process while maintaining all necessary electrical connections.
2Productivity
If gate contact, source/drain contact, and bottom via are formed through separate fabrication processes, then each component can be precisely controlled, but the overall manufacturing time and process steps increase
Solution Approach 1:
The patent combines the formation of gate contact, source/drain contact, and bottom via into a single unified fabrication process. This merging eliminates multiple sequential process steps, reducing the total fabrication time and improving manufacturing efficiency without sacrificing the precision needed for each electrical connection.
3Reliability
If multiple separate contacts and vias are formed, then electrical connections can be independently optimized, but the number of fabrication steps and process variations increase
Solution Approach 1:
The patent integrates multiple electrical connections into a single contact structure that is formed through one fabrication process. This approach reduces the number of process steps and minimizes process variations, making manufacturing simpler while maintaining reliable electrical connections through the unified design.
Data Source
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AI summary
A semiconductor device comprising a first lower interlayer insulating layer, an insulating pattern extending in a first horizontal direction, a first and second plurality of nanosheets stacked apart from one another in a vertical direction, a first gate electrode extending in a second horizontal direction, the first gate electrode surrounding the first plurality of nanosheets, a second gate electrode extending in the second horizontal direction, the second gate electrode surrounding the second plurality of nanosheets, a source/drain region between the first and second gate electrodes, a source/drain contact penetrating the first lower interlayer insulating layer and the insulating pattern, the source/drain contact electrically connected to the source/drain region, and a gate contact penetrating the first lower interlayer insulating layer and the insulating pattern, the gate contact electrically connected to the second gate electrode, at least a portion of a sidewall of the gate contact contacting the source/drain contact.