Integrated N-P Thin Film Transistor for Compact CMOS Inverters
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Solution Overview
Problem
Current display devices, such as LCD and OLED, face limitations in size reduction due to the requirement of both N-type and P-type MOSFETs for CMOS inverters, which complicates the manufacturing process and hinders the development of smaller, more efficient thin film transistors.
Innovation Solution
A thin film transistor design that integrates both N-type and P-type semiconductor layers, formed under the same vacuum conditions within one chamber, with the P-type layer being thinner than the N-type layer, allowing for both N-type and P-type semiconductor properties in a single layer, enabling efficient channel formation and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both N-type and P-type MOSFETs are used for CMOS inverters, then the display device can operate properly with appropriate signal outputting, but the device size cannot be reduced and the manufacturing process becomes complicated
Solution Approach 1:
The patent combines both N-type and P-type semiconductor layers within a single thin film transistor structure. The N-type semiconductor layer and P-type semiconductor layer are formed in different regions of the same active area, allowing one TFT to replace the traditional separate N-type and P-type MOSFETs required for CMOS inverters, thereby simplifying the manufacturing process while maintaining proper signal outputting capability
Solution Approach 2:
The thin film transistor structure is designed to perform multiple functions by integrating both N-type and P-type semiconductor properties in one device. This universal structure can function as both N-type and P-type transistors depending on which semiconductor layer is activated, eliminating the need for separate dedicated N-type and P-type MOSFET fabrication processes
2Reliability
If both N-type and P-type MOSFETs are used for CMOS inverters, then the display device can operate properly with appropriate signal outputting, but the device size increases
Solution Approach 1:
The patent merges the functionality of separate N-type and P-type MOSFETs into a single thin film transistor by stacking the N-type semiconductor layer and P-type semiconductor layer within the same active area. This integration allows the display device to maintain proper signal outputting capability while significantly reducing the overall device size compared to traditional CMOS inverter structures requiring separate transistors
3Reliability
If the P-type semiconductor layer is made thinner, then the mobility and performance of the P-type layer is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the thickness parameter of the P-type semiconductor layer to be thinner than the N-type semiconductor layer. This parameter change improves the mobility and electrical performance of the P-type layer. The invention addresses the increased manufacturing precision requirements through careful process design and control during the sequential formation of the N-type and P-type semiconductor layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the mobility and reduces the threshold voltage of the P-type semiconductor layer, improving the overall performance and size efficiency of the thin film transistor, allowing for more compact and effective display devices.
Implementation Method 1
both N-type and P-type semiconductor layers, which are formed under the same vacuum condition within one chamber
Data Source
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AI summary
Disclosed is a thin film transistor (10) including both an N-type semiconductor layer (131) and a P-type semiconductor layer (132), a method for manufacturing the same, and a display device (1000) including the same, wherein the thin film transistor (10) may include a first gate electrode (110) on a substrate (100); a first gate insulating film (120) for covering the first gate electrode (110); a semiconductor layer (130) on the first gate insulating film (129); a second gate insulating film (150) covering the semiconductor layer (130); and a second gate electrode (160) on the second gate insulating film (150), wherein the semiconductor layer (130) includes the N-type semiconductor layer (131) and the P-type semiconductor layer (132).