Integrated OTP Memory Cells With Protected Shared Array Writes
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Solution Overview
Problem
Existing memory devices face challenges in reducing area and manufacturing costs due to the separation of normal cells and OTP cells in different memory cell arrays, which also leads to increased vulnerability of normal cells during OTP write operations.
Innovation Solution
A memory device design where normal cells and OTP cells are integrated in a single memory cell array, using distinct reference resistances to minimize the impact of OTP write operations on normal cells, with a write driver performing multiple write operations to ensure successful programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal cells and OTP cells are disposed in independent memory cell arrays, then the high voltage for OTP write operations does not affect normal cells, but the area of the memory cell array, write driver, and manufacturing costs increase
Solution Approach 1:
The patent merges normal cells and OTP cells into a single memory cell array, eliminating the need for separate arrays. This integration reduces the overall area while implementing sharing mechanisms for bit lines and write drivers between normal and OTP cells, thereby reducing the area of supporting circuitry as well.
Solution Approach 2:
The patent implements multi-functionality by enabling the write driver and bit lines to serve both normal cells and OTP cells. The write driver can operate in different modes (normal write mode and OTP write mode) and the bit lines are shared between the two cell types, allowing these components to perform multiple functions and reducing the total component count and area.
2Reliability
If normal cells and OTP cells are disposed in independent memory cell arrays, then the high voltage for OTP write operations does not affect normal cells, but the area of the write driver and manufacturing costs increase
Solution Approach 1:
The patent merges normal cells and OTP cells into a single memory cell array, eliminating the need for separate arrays. This integration reduces the overall area while implementing sharing mechanisms for bit lines and write drivers between normal and OTP cells, thereby reducing the area of supporting circuitry as well.
Solution Approach 2:
The patent implements multi-functionality by enabling the write driver and bit lines to serve both normal cells and OTP cells. The write driver can operate in different modes (normal write mode and OTP write mode) and the bit lines are shared between the two cell types, allowing these components to perform multiple functions and reducing the total component count and area.
3Area of stationary object
If normal cells and OTP cells are integrated in one memory cell array, then the area and manufacturing costs are reduced, but the high voltage for OTP write operations may affect adjacent normal cells
Solution Approach 1:
The patent applies local quality by selectively applying different voltages to different regions. During OTP write operations, high voltage is applied only to selected OTP cells while adjacent normal cells receive different voltage levels. The patent also applies different reference resistances (first reference resistance for normal cells, second reference resistance for OTP cells) to locally differentiate the electrical characteristics of the two cell types within the same array.
Solution Approach 2:
The patent introduces control circuitry as an intermediary that manages voltage application and selection between normal cells and OTP cells. This control mechanism ensures that during OTP write operations, only the intended OTP cells receive the high breakdown voltage while adjacent normal cells are protected through selective switching and voltage control.
4Area of stationary object
If normal cells and OTP cells are integrated in one memory cell array, then the area and manufacturing costs are reduced, but the high voltage for OTP write operations may affect adjacent normal cells
Solution Approach 1:
The patent applies local quality by selectively applying different voltages to different regions. During OTP write operations, high voltage is applied only to selected OTP cells while adjacent normal cells receive different voltage levels. The patent also applies different reference resistances (first reference resistance for normal cells, second reference resistance for OTP cells) to locally differentiate the electrical characteristics of the two cell types within the same array.
Solution Approach 2:
The patent introduces control circuitry as an intermediary that manages voltage application and selection between normal cells and OTP cells. This control mechanism ensures that during OTP write operations, only the intended OTP cells receive the high breakdown voltage while adjacent normal cells are protected through selective switching and voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration reduces the device area and manufacturing costs while enhancing the durability and reliability of the memory device by minimizing the influence of OTP cells on normal cells.
Implementation Method 1
A resistance value of the MTJ element may vary depending on magnetization directions of two magnetic materials. For example, the MTJ element may have a great resistance value when the magnetization directions of two magnetic materials are anti-parallel to each other and may have a small resistance value when the magnetization directions of two magnetic materials are parallel to each other.
Implementation Method 2
The OTP cells may be implemented by applying a high voltage to a conventional MTJ element such that the breakdown is caused
Data Source
AI summary
A memory device may include a memory cell array, a write driver, and a sensing circuit. The memory cell array may include a normal cell connected to a bit line and a one time programmable (OTP) cell connected to the bit line. A program state of the normal cell may be determined by a first reference resistance and a program state of the OTP cell may be determined by a second reference resistance smaller than the first reference resistance. The write driver may perform a first OTP write operation on the OTP cell, and a sensing circuit may determine whether the first OTP write operation on the OTP cell is passed. The write driver may perform a second OTP write operation on the OTP cell experiencing a failure of the first OTP write operation.