Integrated Overlay Mark for LELE Double Patterning Lithography

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Solution Overview

Problem

In the LELE-type double patterning lithography process, the accuracy of overlay error measurement is compromised due to the requirement of a larger wafer area and lower measurement accuracy caused by measuring overlay errors between different parts of linear patterns in separate overlay marks.

Innovation Solution

The overlay mark is designed with first x-directional and y-directional patterns of a previous layer and alternately arranged second and third x-directional and y-directional patterns of the current layer, formed in the same overlay mark, allowing for reduced wafer area usage and improved measurement accuracy by assessing overlay errors against the same patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If overlay marks are formed with separate regions for first and second lithography steps, then each lithography step can be measured independently, but the wafer area required increases and measurement accuracy decreases

Engineering Contradiction:
Improveoverlay error measurement accuracyVSAvoidwafer area required
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent merges the overlay mark regions for the first and second lithography steps into a single integrated overlay mark structure. The first overlay mark and second overlay mark are formed in the same physical region on the wafer, allowing both lithography steps to be measured against the same reference patterns. This consolidation reduces the total wafer area required while improving measurement accuracy by eliminating variations between separate mark regions.

Inventive Principle:
Principle #5Merging (Combining)

2Manufacturing precision

If overlay marks use separate regions for different lithography steps, then pattern formation can proceed independently, but the alignment accuracy between steps deteriorates

Engineering Contradiction:
Improvealignment accuracyVSAvoidoverlay mark structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The overlay mark is segmented into distinct functional components: first overlay mark patterns from the previous layer, second overlay mark patterns from the first lithography step, and third overlay mark patterns from the second lithography step. These segmented elements are arranged in a specific alternating sequence within the same physical region, allowing independent measurement of each lithography step while maintaining consistent reference standards for high alignment accuracy.

Inventive Principle:
Principle #1Segmentation

3Productivity

If linear patterns are formed in separate overlay mark regions, then each region can be optimized for its specific lithography step, but the overall process efficiency decreases

Engineering Contradiction:
Improveprocess efficiencyVSAvoidoverlay error measurement accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The integrated overlay mark structure serves multiple functions simultaneously: it provides reference patterns for both the first and second lithography steps, enables measurement of overlay errors for both steps, and maintains consistent alignment standards across the entire double patterning process. This multi-functional design eliminates the need for separate optimization of different mark regions, improving process efficiency without sacrificing measurement precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9305884B1Overlay mark and method for forming the same
Publication Date: 2016.04.05 UNITED MICROELECTRONICS CORP
  • US9305884B1 patent drawing
  • US9305884B1 patent drawing

AI summary

An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.