Integrated Package Hermetic Sealing via Lateral Substrate Integration
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Solution Overview
Problem
The increasing demand for thinner packages and the need for hermetic sealing of sensitive elements, such as MEMS devices, in system-in-package (SIP) applications is hindered by the thickness of existing hermetic packaging solutions like chip scale packaging and wafer level packaging, which compromise the inclusion of these devices in modules.
Innovation Solution
An integrated semiconductor device is created using a device substrate with a semiconductor element and conductive connectors, mounted on an interconnection substrate with a sealing recess and ring, forming a sealed cavity without increasing the overall thickness, allowing for hermetic sealing similar to bare die configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip scale packaging or wafer level packaging is used to provide hermetic sealing, then the sensitive element is hermetically sealed, but the device thickness increases significantly
Solution Approach 1:
The patent transitions from vertical stacking (increasing thickness) to lateral integration (increasing area utilization). Multiple semiconductor devices are mounted on the same substrate in a planar arrangement, with electrical connections routed through conductive vias and trace patterns on the substrate surface, eliminating the need for vertical layering and reducing overall package thickness.
Solution Approach 2:
The patent combines multiple semiconductor devices, hermetic sealing structures, and electrical interconnection systems into a single integrated package. The substrate serves as a common platform that simultaneously provides mechanical support, electrical interconnection, and hermetic sealing, merging multiple functions into one unified structure.
2Reliability
If hermetic enclosure is added to package sensitive elements, then protection is provided, but the package becomes thicker and harder to include in SIP
Solution Approach 1:
The substrate performs multiple functions simultaneously: it provides mechanical support for mounting devices, establishes electrical connections through conductive patterns and vias, and creates hermetic sealing enclosures. This multi-functionality reduces the need for separate dedicated components and simplifies the overall package structure.
Solution Approach 2:
The hermetic sealing is achieved by dividing the package into multiple sealed cavities, each containing individual sensitive elements. The substrate is segmented into multiple regions with separate sealing structures, allowing independent protection of each device while maintaining a compact overall structure.
3Reliability
If conventional hermetic packaging is used, then sealing is achieved, but the size and thickness compromise inclusion in module
Solution Approach 1:
The patent utilizes the substrate surface area efficiently by arranging multiple devices and connection points in a planar configuration. Electrical connections are routed through two-dimensional trace patterns and vias on the substrate surface, maximizing area utilization while maintaining a thin profile.
Solution Approach 2:
The electrical interconnection system employs flexible routing with conductive traces that can adapt to different device configurations. The trace patterns and via placements can be dynamically adjusted during design to optimize space utilization and connection efficiency for different package layouts.
Data Source
AI summary
A device substrate has a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface. An interconnection substrate has an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring. The device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element. Electrical interconnects extend across the interconnection major surface. Interconnection bumps are provided outside the sealing ring to electrically connect the device to the interconnect substrate.