Integrated Circuit Paged Buffering for Parallel FEC Decoding
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Solution Overview
Problem
Existing integrated circuits for decoding data encoded with FEC codes, particularly in IoT devices with limited power and processing capabilities, face inefficiencies due to the use of First-In-First-Out (FIFO) buffers that require sequential operations and consume additional clock cycles for random access, leading to increased resource consumption and reduced decoding efficiency.
Innovation Solution
Implementing paged buffering with shared random access memory (RAM) and counters for upstream and downstream processors, allowing direct communication and reducing the need for flag checks, enabling parallel processing and efficient data transfer without additional clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FIFO buffers are used for data processing, then data transfer is simplified, but processing speed decreases due to sequential operations and additional clock cycles
Solution Approach 1:
The patent segments the buffer memory into multiple pages, allowing the upstream processor to write to one page while the downstream processor reads from another page. This segmentation enables parallel access patterns that overcome the sequential nature of traditional FIFO buffers, improving processing speed without requiring complex buffer management protocols.
Solution Approach 2:
The patent introduces a new dimension to buffer management by using page-level addressing instead of traditional sequential FIFO pointers. This dimensional change from linear sequential access to multi-page parallel access allows both processors to operate simultaneously on different pages, resolving the speed-complexity contradiction.
2Productivity
If random access to buffer data is implemented, then processing efficiency improves, but additional clock cycles are consumed for address management
Solution Approach 1:
The patent performs preliminary actions by pre-organizing buffer data into fixed-size pages with predetermined addresses. This preliminary structuring allows the downstream processor to directly access required data pages without iterative pointer chasing or flag checking, improving decoding efficiency while minimizing clock cycle overhead through predictable access patterns.
Solution Approach 2:
The patent introduces page address counters as intermediaries that automatically track the current read and write pages. These counters serve as mediators between the processors and the buffer memory, enabling efficient random access to data pages without requiring complex address management logic, thus improving productivity while reducing time loss.
3Productivity
If shared RAM with paged buffering is used, then parallel processing is enabled, but memory management complexity increases
Solution Approach 1:
The patent implements self-service memory management where the page address counters automatically increment and manage page allocation without external intervention. The upstream and downstream processors independently manage their respective page counters, enabling parallel processing while keeping memory management simple and decentralized, thus avoiding increased complexity.
Data Source
AI summary
Integrated circuit data stream processing utilizing paged buffering is performed by an integrated circuit that includes an upstream random access memory, a local read counter, a downstream random access memory, a local write counter, and a processor. The local read counter is configured to store a value indicating whether any accessible blocks of data are stored in the upstream memory. The local write counter is configured to store a value indicating whether any downstream pages of the downstream memory are available for recording. The processor is configured to adjust the local read counter to indicate a page release, adjust the local write counter to indicate a page occupy, read a first block of data recorded to the upstream memory, process the first block of data to produce a second block of data, and record the second block of data to the downstream memory.