Integrated PCIe Controller Power Management Logic
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Solution Overview
Problem
Conventional computing systems lack a procedure to power down integrated PCIe controllers during ongoing processor operations, leading to inefficiencies in power management, especially when transitioning to lower power states.
Innovation Solution
A processor circuit with an integrated PCIe controller and logic to detect power reduction triggers, disable the PCIe controller, and remove power based on a power removal setting, using power gates to manage power distribution and activate alternative devices to maintain functionality at reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the integrated PCIe controller remains powered during processor operation, then the PCIe link functionality is maintained, but power consumption increases and prevents the processor from entering lower power states
Solution Approach 1:
The system performs preliminary actions by detecting power reduction triggers before actually reducing power, storing configuration information and activating alternative devices in advance. This allows the PCIe controller to be powered down smoothly without losing functionality, enabling the processor to enter lower power states while maintaining essential features through alternative devices.
Solution Approach 2:
The patent introduces an intermediary mechanism (alternative device activation) that mediates between the powered-down PCIe controller and the system's need for PCIe functionality. When the PCIe controller is powered off, alternative devices are activated to provide essential features, thus maintaining adaptability while reducing power consumption.
2Use of energy by moving object
If power is removed from the integrated PCIe controller, then the processor can enter lower power states, but the PCIe link functionality is lost
Solution Approach 1:
Before removing power from the PCIe controller, the system performs preliminary actions including detecting power reduction triggers, storing configuration information, and activating alternative devices. This preliminary preparation ensures that PCIe link functionality is maintained through alternative means even after the controller is powered down, thus maintaining reliability while reducing power consumption.
Solution Approach 2:
The system changes the operational parameters of the PCIe subsystem by transitioning from an active PCIe controller to a powered-off state with alternative device activation. This parameter change allows the system to maintain essential functionality while operating in a lower power state, resolving the contradiction between power consumption and functional reliability.
3Use of energy by moving object
If conventional approaches are used to disable the PCIe controller, then power consumption is reduced, but no procedure exists to power down the controller during ongoing operation
Solution Approach 1:
The patent establishes a complete power management procedure by performing preliminary actions before power reduction. The system detects power reduction triggers, stores configuration information, activates alternative devices, and then safely powers down the PCIe controller. This structured preliminary preparation makes the power management process straightforward and reliable, enabling easy transition to lower power states during ongoing operation.
Solution Approach 2:
The patent introduces dynamic power management that allows the PCIe controller to transition between powered and powered-off states during ongoing operation. The system dynamically detects power reduction triggers and adjusts power consumption accordingly, making the power management procedure flexible and adaptable to different operational conditions rather than being static.
Data Source
AI summary
Improved power control techniques for integrated peripheral component interconnect express (PCIe) controllers are described. In one embodiment, for example, a processor circuit may comprise an integrated PCIe controller and logic to detect a power reduction trigger, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller. Other embodiments are described and claimed.